@@ -21800,17 +21800,14 @@ SDValue tryLowerPartialReductionToDot(SDNode *N,
21800
21800
if (A.getValueType() != B.getValueType())
21801
21801
return SDValue();
21802
21802
21803
- unsigned DotIntrinsicId = Intrinsic::not_intrinsic ;
21803
+ unsigned Opcode = 0 ;
21804
21804
21805
21805
if (IsSExt)
21806
- DotIntrinsicId = Intrinsic::aarch64_sve_sdot ;
21806
+ Opcode = AArch64ISD::SDOT ;
21807
21807
else if (IsZExt)
21808
- DotIntrinsicId = Intrinsic::aarch64_sve_udot;
21809
-
21810
- assert(DotIntrinsicId != Intrinsic::not_intrinsic &&
21811
- "Unexpected dot product case encountered.");
21808
+ Opcode = AArch64ISD::UDOT;
21812
21809
21813
- auto IntrinsicId = DAG.getConstant(DotIntrinsicId, DL, MVT::i64 );
21810
+ assert(Opcode != 0 && "Unexpected dot product case encountered." );
21814
21811
21815
21812
// The fully-reduced type. Should be a vector of i32 or i64
21816
21813
EVT ReducedType = N->getValueType(0);
@@ -21824,13 +21821,13 @@ SDValue tryLowerPartialReductionToDot(SDNode *N,
21824
21821
// as many elements in the wide type
21825
21822
if (WideType == MVT::nxv16i32 && ReducedType == MVT::nxv4i32 &&
21826
21823
ExtendedType == MVT::nxv16i8)
21827
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN , DL, MVT::nxv4i32,
21828
- {IntrinsicId, NarrowOp, A, B} );
21824
+ return DAG.getNode(Opcode , DL, MVT::nxv4i32,
21825
+ NarrowOp, A, B);
21829
21826
21830
21827
if (WideType == MVT::nxv8i64 && ReducedType == MVT::nxv2i64 &&
21831
21828
ExtendedType == MVT::nxv8i16)
21832
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN , DL, MVT::nxv2i64,
21833
- {IntrinsicId, NarrowOp, A, B} );
21829
+ return DAG.getNode(Opcode , DL, MVT::nxv2i64,
21830
+ NarrowOp, A, B);
21834
21831
21835
21832
return SDValue();
21836
21833
}
0 commit comments