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Commit 31b7567

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Emit a node instead of an intrinsic
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+8
-11
lines changed

1 file changed

+8
-11
lines changed

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -21800,17 +21800,14 @@ SDValue tryLowerPartialReductionToDot(SDNode *N,
2180021800
if (A.getValueType() != B.getValueType())
2180121801
return SDValue();
2180221802

21803-
unsigned DotIntrinsicId = Intrinsic::not_intrinsic;
21803+
unsigned Opcode = 0;
2180421804

2180521805
if (IsSExt)
21806-
DotIntrinsicId = Intrinsic::aarch64_sve_sdot;
21806+
Opcode = AArch64ISD::SDOT;
2180721807
else if (IsZExt)
21808-
DotIntrinsicId = Intrinsic::aarch64_sve_udot;
21809-
21810-
assert(DotIntrinsicId != Intrinsic::not_intrinsic &&
21811-
"Unexpected dot product case encountered.");
21808+
Opcode = AArch64ISD::UDOT;
2181221809

21813-
auto IntrinsicId = DAG.getConstant(DotIntrinsicId, DL, MVT::i64);
21810+
assert(Opcode != 0 && "Unexpected dot product case encountered.");
2181421811

2181521812
// The fully-reduced type. Should be a vector of i32 or i64
2181621813
EVT ReducedType = N->getValueType(0);
@@ -21824,13 +21821,13 @@ SDValue tryLowerPartialReductionToDot(SDNode *N,
2182421821
// as many elements in the wide type
2182521822
if (WideType == MVT::nxv16i32 && ReducedType == MVT::nxv4i32 &&
2182621823
ExtendedType == MVT::nxv16i8)
21827-
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::nxv4i32,
21828-
{IntrinsicId, NarrowOp, A, B});
21824+
return DAG.getNode(Opcode, DL, MVT::nxv4i32,
21825+
NarrowOp, A, B);
2182921826

2183021827
if (WideType == MVT::nxv8i64 && ReducedType == MVT::nxv2i64 &&
2183121828
ExtendedType == MVT::nxv8i16)
21832-
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::nxv2i64,
21833-
{IntrinsicId, NarrowOp, A, B});
21829+
return DAG.getNode(Opcode, DL, MVT::nxv2i64,
21830+
NarrowOp, A, B);
2183421831

2183521832
return SDValue();
2183621833
}

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