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1 parent cd116ee commit 31bd7a5Copy full SHA for 31bd7a5
llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
@@ -1,8 +1,11 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xsfmclic -o - %s \
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-; RUN: | FileCheck %s --check-prefix=RV32
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple riscv64-unknown-elf -mattr=+experimental-xsfmclic -o - %s \
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-; RUN: | FileCheck %s --check-prefix=RV64
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64
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+
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+;; These are failing to verify.
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+; XFAIL: *
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; Test Handling of the SiFive-CLIC interrupt attributes.
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;
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