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Simon Moll
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[VE] Packed v512f32 binop isel and tests
Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D118335
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‎llvm/lib/Target/VE/VVPInstrPatternsVec.td

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@@ -237,6 +237,13 @@ defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv,
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f64, v256f64, "VFDIVD",
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f32, v256f32, "VFDIVS">;
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defm : Binary_rv_vv<c_vvp_fadd,
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i64, v512f32, v512i1, "PVFADD">;
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defm : Binary_rv_vv<c_vvp_fmul,
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i64, v512f32, v512i1, "PVFMUL">;
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defm : Binary_rv_vv<vvp_fsub,
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i64, v512f32, v512i1, "PVFSUB">;
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multiclass Merge_mvv<
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SDPatternOperator OpNode,
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ValueType DataVT, ValueType MaskVT,

‎llvm/test/CodeGen/VE/Packed/vp_fadd.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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declare <512 x float> @llvm.vp.fadd.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
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define fastcc <512 x float> @test_vp_fadd_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fadd_v512f32_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, 1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvfadd %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}
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define fastcc <512 x float> @test_vp_fadd_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fadd_v512f32_rv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s2, %s0, (32)1
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfadd %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <512 x float> undef, float %s0, i32 0
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%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}
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define fastcc <512 x float> @test_vp_fadd_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fadd_v512f32_vr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s2, %s0, (32)1
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfadd %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <512 x float> undef, float %s1, i32 0
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%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x float> @llvm.vp.fadd.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}

‎llvm/test/CodeGen/VE/Packed/vp_fmul.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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declare <512 x float> @llvm.vp.fmul.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
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define fastcc <512 x float> @test_vp_fmul_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fmul_v512f32_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, 1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvfmul %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}
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define fastcc <512 x float> @test_vp_fmul_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fmul_v512f32_rv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s2, %s0, (32)1
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <512 x float> undef, float %s0, i32 0
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%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}
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define fastcc <512 x float> @test_vp_fmul_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fmul_v512f32_vr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s2, %s0, (32)1
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfmul %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <512 x float> undef, float %s1, i32 0
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%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x float> @llvm.vp.fmul.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}

‎llvm/test/CodeGen/VE/Packed/vp_fsub.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
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declare <512 x float> @llvm.vp.fsub.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
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define fastcc <512 x float> @test_vp_fsub_v512f32_vv(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fsub_v512f32_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, 1, %s0
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvfsub %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}
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define fastcc <512 x float> @test_vp_fsub_v512f32_rv(float %s0, <512 x float> %i1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fsub_v512f32_rv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s2, %s0, (32)1
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: adds.w.sx %s1, 1, %s1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: srl %s1, %s1, 1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pvfsub %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <512 x float> undef, float %s0, i32 0
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%i0 = shufflevector <512 x float> %xins, <512 x float> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}
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define fastcc <512 x float> @test_vp_fsub_v512f32_vr(<512 x float> %i0, float %s1, <512 x i1> %m, i32 %n) {
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; CHECK-LABEL: test_vp_fsub_v512f32_vr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s2, %s0, (32)1
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; CHECK-NEXT: srl %s0, %s0, 32
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; CHECK-NEXT: or %s0, %s0, %s2
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vbrd %v1, %s0
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; CHECK-NEXT: adds.w.sx %s0, 1, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: srl %s0, %s0, 1
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: pvfsub %v0, %v0, %v1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <512 x float> undef, float %s1, i32 0
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%i1 = shufflevector <512 x float> %yins, <512 x float> undef, <512 x i32> zeroinitializer
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%r0 = call <512 x float> @llvm.vp.fsub.v512f32(<512 x float> %i0, <512 x float> %i1, <512 x i1> %m, i32 %n)
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ret <512 x float> %r0
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}

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