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[RISCV] Mark pointer masking extensions as non-experimental
These extensions were ratified very recently. <https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions> I've ensured we have definitions for all extensions in the document <https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link>. There are no additional CSRs.
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‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -120,20 +120,25 @@
120120
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
121121
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
122122
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
123+
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
124+
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
123125
// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
124126
// CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level)
125127
// CHECK-NEXT: ssccfg 1.0 'Ssccfg' (Counter Configuration Supervisor Level)
126128
// CHECK-NEXT: ssccptr 1.0 'Ssccptr' (Main memory supports page table reads)
127129
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
128130
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
129131
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
132+
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
133+
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
130134
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
131135
// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
132136
// CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present)
133137
// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts)
134138
// CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values)
135139
// CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode)
136140
// CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported)
141+
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
137142
// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits)
138143
// CHECK-NEXT: svadu 1.0 'Svadu' (Hardware A/D updates)
139144
// CHECK-NEXT: svbare 1.0 'Svbare' $(satp mode Bare supported)
@@ -176,12 +181,7 @@
176181
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
177182
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
178183
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
179-
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
180-
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
181184
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
182-
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
183-
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
184-
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
185185
// CHECK-EMPTY:
186186
// CHECK-NEXT: Supported Profiles
187187
// CHECK-NEXT: rva20s64

‎clang/test/Driver/riscv-profiles.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@
195195
// RVA23S64: "-target-feature" "+ssccptr"
196196
// RVA23S64: "-target-feature" "+sscofpmf"
197197
// RVA23S64: "-target-feature" "+sscounterenw"
198-
// RVA23S64: "-target-feature" "+experimental-ssnpm"
198+
// RVA23S64: "-target-feature" "+ssnpm"
199199
// RVA23S64: "-target-feature" "+ssstateen"
200200
// RVA23S64: "-target-feature" "+sstc"
201201
// RVA23S64: "-target-feature" "+sstvala"

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1710,10 +1710,10 @@
17101710
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
17111711
// CHECK-ZICFISS-EXT: __riscv_zicfiss 1000000{{$}}
17121712

1713-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1713+
// RUN: %clang --target=riscv32 \
17141714
// RUN: -march=rv32i_ssnpm1p0 -E -dM %s \
17151715
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
1716-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1716+
// RUN: %clang --target=riscv64 \
17171717
// RUN: -march=rv64i_ssnpm1p0 -E -dM %s \
17181718
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
17191719
// CHECK-SSNPM-EXT: __riscv_ssnpm 1000000{{$}}
@@ -1726,26 +1726,26 @@
17261726
// RUN: -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
17271727
// CHECK-SMNPM-EXT: __riscv_smnpm 1000000{{$}}
17281728

1729-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1729+
// RUN: %clang --target=riscv32 \
17301730
// RUN: -march=rv32i_smmpm1p0 -E -dM %s \
17311731
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
1732-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1732+
// RUN: %clang --target=riscv64 \
17331733
// RUN: -march=rv64i_smmpm1p0 -E -dM %s \
17341734
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
17351735
// CHECK-SMMPM-EXT: __riscv_smmpm 1000000{{$}}
17361736

1737-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1737+
// RUN: %clang --target=riscv32 \
17381738
// RUN: -march=rv32i_sspm1p0 -E -dM %s \
17391739
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
1740-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1740+
// RUN: %clang --target=riscv64 \
17411741
// RUN: -march=rv64i_sspm1p0 -E -dM %s \
17421742
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
17431743
// CHECK-SSPM-EXT: __riscv_sspm 1000000{{$}}
17441744

1745-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1745+
// RUN: %clang --target=riscv32 \
17461746
// RUN: -march=rv32i_supm1p0 -E -dM %s \
17471747
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
1748-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1748+
// RUN: %clang --target=riscv64 \
17491749
// RUN: -march=rv64i_supm1p0 -E -dM %s \
17501750
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
17511751
// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}

‎llvm/docs/RISCVUsage.rst

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -129,20 +129,25 @@ on support follow.
129129
``Smcdeleg`` Supported
130130
``Smcsrind`` Supported
131131
``Smepmp`` Supported
132+
``Smmpm`` Supported
133+
``Smnpm`` Supported
132134
``Smstateen`` Assembly Support
133135
``Ssaia`` Supported
134136
``Ssccfg`` Supported
135137
``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
136138
``Sscofpmf`` Assembly Support
137139
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
138140
``Sscsrind`` Supported
141+
``Ssnpm`` Supported
142+
``Sspm`` Supported
139143
``Ssqosid`` Assembly Support
140144
``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
141145
``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
142146
``Sstc`` Assembly Support
143147
``Sstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
144148
``Sstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
145149
``Ssu64xl`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
150+
``Supm`` Supported
146151
``Svade`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
147152
``Svadu`` Assembly Support
148153
``Svbare`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
@@ -307,9 +312,6 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
307312

308313
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
309314

310-
``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
311-
LLVM implements the `v1.0.0-rc2 specification <https://github.com/riscv/riscv-j-extension/releases/tag/pointer-masking-v1.0.0-rc2>`__.
312-
313315
``experimental-zalasr``
314316
LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__.
315317

‎llvm/docs/ReleaseNotes.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,8 @@ Changes to the RISC-V Backend
171171
* Added `Smctr` and `Ssctr` extensions.
172172
* `-mcpu=syntacore-scr7` was added.
173173
* The `Zacas` extension is no longer marked as experimental.
174+
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
175+
are no longer marked as experimental.
174176

175177
Changes to the WebAssembly Backend
176178
----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1028,33 +1028,33 @@ def FeatureStdExtSvpbmt
10281028
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
10291029
// present.
10301030
def FeatureStdExtSsnpm
1031-
: RISCVExperimentalExtension<"ssnpm", 1, 0,
1032-
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
1031+
: RISCVExtension<"ssnpm", 1, 0,
1032+
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
10331033

10341034
// A machine-level extension that provides pointer masking for the next lower
10351035
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
10361036
def FeatureStdExtSmnpm
1037-
: RISCVExperimentalExtension<"smnpm", 1, 0,
1038-
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
1037+
: RISCVExtension<"smnpm", 1, 0,
1038+
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
10391039

10401040
// A machine-level extension that provides pointer masking for M-mode.
10411041
def FeatureStdExtSmmpm
1042-
: RISCVExperimentalExtension<"smmpm", 1, 0,
1043-
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;
1042+
: RISCVExtension<"smmpm", 1, 0,
1043+
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;
10441044

10451045
// An extension that indicates that there is pointer-masking support available
10461046
// in supervisor mode, with some facility provided in the supervisor execution
10471047
// environment to control pointer masking.
10481048
def FeatureStdExtSspm
1049-
: RISCVExperimentalExtension<"sspm", 1, 0,
1050-
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
1049+
: RISCVExtension<"sspm", 1, 0,
1050+
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
10511051

10521052
// An extension that indicates that there is pointer-masking support available
10531053
// in user mode, with some facility provided in the application execution
10541054
// environment to control pointer masking.
10551055
def FeatureStdExtSupm
1056-
: RISCVExperimentalExtension<"supm", 1, 0,
1057-
"'Supm' (Indicates User-mode Pointer Masking)">;
1056+
: RISCVExtension<"supm", 1, 0,
1057+
"'Supm' (Indicates User-mode Pointer Masking)">;
10581058

10591059
def FeatureStdExtSmctr
10601060
: RISCVExperimentalExtension<"smctr", 1, 0,

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -128,11 +128,11 @@
128128
; RUN: llc -mtriple=riscv32 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s
129129
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV32ZVBC32E %s
130130
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV32ZVKGS %s
131-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s
132-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s
133-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
134-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
135-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
131+
; RUN: llc -mtriple=riscv32 -mattr=+ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s
132+
; RUN: llc -mtriple=riscv32 -mattr=+smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s
133+
; RUN: llc -mtriple=riscv32 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
134+
; RUN: llc -mtriple=riscv32 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
135+
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
136136
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
137137
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
138138

@@ -270,11 +270,11 @@
270270
; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s
271271
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV64ZVBC32E %s
272272
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV64ZVKGS %s
273-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s
274-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s
275-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
276-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
277-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
273+
; RUN: llc -mtriple=riscv64 -mattr=+ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s
274+
; RUN: llc -mtriple=riscv64 -mattr=+smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s
275+
; RUN: llc -mtriple=riscv64 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
276+
; RUN: llc -mtriple=riscv64 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
277+
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
278278
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
279279
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
280280

‎llvm/test/CodeGen/RISCV/rvv/pr107950.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,5 +26,5 @@ entry:
2626
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
2727
declare <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr>, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
2828

29-
attributes #0 = { "target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-experimental-smmpm,-experimental-smnpm,-experimental-ssctr,-experimental-ssnpm,-experimental-sspm,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
29+
attributes #0 = { "target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-smmpm,-smnpm,-experimental-ssctr,-ssnpm,-sspm,-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
3030
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1065,20 +1065,25 @@ R"(All available -march extensions for RISC-V
10651065
smcdeleg 1.0
10661066
smcsrind 1.0
10671067
smepmp 1.0
1068+
smmpm 1.0
1069+
smnpm 1.0
10681070
smstateen 1.0
10691071
ssaia 1.0
10701072
ssccfg 1.0
10711073
ssccptr 1.0
10721074
sscofpmf 1.0
10731075
sscounterenw 1.0
10741076
sscsrind 1.0
1077+
ssnpm 1.0
1078+
sspm 1.0
10751079
ssqosid 1.0
10761080
ssstateen 1.0
10771081
ssstrict 1.0
10781082
sstc 1.0
10791083
sstvala 1.0
10801084
sstvecd 1.0
10811085
ssu64xl 1.0
1086+
supm 1.0
10821087
svade 1.0
10831088
svadu 1.0
10841089
svbare 1.0
@@ -1121,12 +1126,7 @@ Experimental extensions
11211126
zvbc32e 0.7
11221127
zvkgs 0.7
11231128
smctr 1.0
1124-
smmpm 1.0
1125-
smnpm 1.0
11261129
ssctr 1.0
1127-
ssnpm 1.0
1128-
sspm 1.0
1129-
supm 1.0
11301130
11311131
Supported Profiles
11321132
rva20s64

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