@@ -67,61 +67,24 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
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}
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define i64 @rotl_i64 (i64 %x , i64 %z ) {
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- ; SCALAR-LABEL: rotl_i64:
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- ; SCALAR: @ %bb.0:
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- ; SCALAR-NEXT: .save {r4, r5, r11, lr}
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- ; SCALAR-NEXT: push {r4, r5, r11, lr}
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- ; SCALAR-NEXT: rsb r3, r2, #0
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- ; SCALAR-NEXT: and r4, r2, #63
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- ; SCALAR-NEXT: and lr, r3, #63
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- ; SCALAR-NEXT: rsb r3, lr, #32
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- ; SCALAR-NEXT: lsl r2, r0, r4
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- ; SCALAR-NEXT: lsr r12, r0, lr
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- ; SCALAR-NEXT: orr r3, r12, r1, lsl r3
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- ; SCALAR-NEXT: subs r12, lr, #32
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- ; SCALAR-NEXT: lsrpl r3, r1, r12
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- ; SCALAR-NEXT: subs r5, r4, #32
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- ; SCALAR-NEXT: movwpl r2, #0
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- ; SCALAR-NEXT: cmp r5, #0
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- ; SCALAR-NEXT: orr r2, r2, r3
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- ; SCALAR-NEXT: rsb r3, r4, #32
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- ; SCALAR-NEXT: lsr r3, r0, r3
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- ; SCALAR-NEXT: orr r3, r3, r1, lsl r4
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- ; SCALAR-NEXT: lslpl r3, r0, r5
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- ; SCALAR-NEXT: lsr r0, r1, lr
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- ; SCALAR-NEXT: cmp r12, #0
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- ; SCALAR-NEXT: movwpl r0, #0
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- ; SCALAR-NEXT: orr r1, r3, r0
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- ; SCALAR-NEXT: mov r0, r2
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- ; SCALAR-NEXT: pop {r4, r5, r11, pc}
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- ;
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- ; NEON-LABEL: rotl_i64:
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- ; NEON: @ %bb.0:
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- ; NEON-NEXT: .save {r4, r5, r11, lr}
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- ; NEON-NEXT: push {r4, r5, r11, lr}
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- ; NEON-NEXT: and r12, r2, #63
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- ; NEON-NEXT: rsb r2, r2, #0
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- ; NEON-NEXT: rsb r3, r12, #32
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- ; NEON-NEXT: and r4, r2, #63
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- ; NEON-NEXT: subs lr, r12, #32
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- ; NEON-NEXT: lsr r3, r0, r3
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- ; NEON-NEXT: lsr r2, r1, r4
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- ; NEON-NEXT: orr r3, r3, r1, lsl r12
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- ; NEON-NEXT: lslpl r3, r0, lr
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- ; NEON-NEXT: subs r5, r4, #32
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- ; NEON-NEXT: movwpl r2, #0
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- ; NEON-NEXT: cmp r5, #0
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- ; NEON-NEXT: orr r2, r3, r2
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- ; NEON-NEXT: lsr r3, r0, r4
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- ; NEON-NEXT: rsb r4, r4, #32
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- ; NEON-NEXT: lsl r0, r0, r12
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- ; NEON-NEXT: orr r3, r3, r1, lsl r4
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- ; NEON-NEXT: lsrpl r3, r1, r5
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- ; NEON-NEXT: cmp lr, #0
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- ; NEON-NEXT: movwpl r0, #0
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- ; NEON-NEXT: mov r1, r2
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- ; NEON-NEXT: orr r0, r0, r3
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- ; NEON-NEXT: pop {r4, r5, r11, pc}
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+ ; CHECK-LABEL: rotl_i64:
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+ ; CHECK: @ %bb.0:
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+ ; CHECK-NEXT: .save {r4, lr}
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+ ; CHECK-NEXT: push {r4, lr}
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+ ; CHECK-NEXT: ands r3, r2, #32
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+ ; CHECK-NEXT: and r12, r2, #31
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+ ; CHECK-NEXT: mov r3, r0
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+ ; CHECK-NEXT: mov r4, #31
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+ ; CHECK-NEXT: movne r3, r1
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+ ; CHECK-NEXT: movne r1, r0
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+ ; CHECK-NEXT: bic r2, r4, r2
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+ ; CHECK-NEXT: lsl lr, r3, r12
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+ ; CHECK-NEXT: lsr r0, r1, #1
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+ ; CHECK-NEXT: lsl r1, r1, r12
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+ ; CHECK-NEXT: lsr r3, r3, #1
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+ ; CHECK-NEXT: orr r0, lr, r0, lsr r2
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+ ; CHECK-NEXT: orr r1, r1, r3, lsr r2
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+ ; CHECK-NEXT: pop {r4, pc}
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%f = call i64 @llvm.fshl.i64 (i64 %x , i64 %x , i64 %z )
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ret i64 %f
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}
@@ -243,31 +206,21 @@ define i32 @rotr_i32(i32 %x, i32 %z) {
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define i64 @rotr_i64 (i64 %x , i64 %z ) {
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; CHECK-LABEL: rotr_i64:
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; CHECK: @ %bb.0:
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- ; CHECK-NEXT: .save {r4, r5, r11, lr}
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- ; CHECK-NEXT: push {r4, r5, r11, lr}
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- ; CHECK-NEXT: and lr, r2, #63
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- ; CHECK-NEXT: rsb r2, r2, #0
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- ; CHECK-NEXT: rsb r3, lr, #32
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- ; CHECK-NEXT: and r4, r2, #63
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- ; CHECK-NEXT: lsr r12, r0, lr
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- ; CHECK-NEXT: orr r3, r12, r1, lsl r3
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- ; CHECK-NEXT: subs r12, lr, #32
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- ; CHECK-NEXT: lsl r2, r0, r4
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- ; CHECK-NEXT: lsrpl r3, r1, r12
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- ; CHECK-NEXT: subs r5, r4, #32
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- ; CHECK-NEXT: movwpl r2, #0
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- ; CHECK-NEXT: cmp r5, #0
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- ; CHECK-NEXT: orr r2, r3, r2
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- ; CHECK-NEXT: rsb r3, r4, #32
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- ; CHECK-NEXT: lsr r3, r0, r3
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- ; CHECK-NEXT: orr r3, r3, r1, lsl r4
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- ; CHECK-NEXT: lslpl r3, r0, r5
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- ; CHECK-NEXT: lsr r0, r1, lr
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- ; CHECK-NEXT: cmp r12, #0
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- ; CHECK-NEXT: movwpl r0, #0
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- ; CHECK-NEXT: orr r1, r0, r3
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- ; CHECK-NEXT: mov r0, r2
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- ; CHECK-NEXT: pop {r4, r5, r11, pc}
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+ ; CHECK-NEXT: ands r3, r2, #32
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+ ; CHECK-NEXT: mov r3, r1
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+ ; CHECK-NEXT: moveq r3, r0
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+ ; CHECK-NEXT: moveq r0, r1
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+ ; CHECK-NEXT: mov r1, #31
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+ ; CHECK-NEXT: lsl r12, r0, #1
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+ ; CHECK-NEXT: bic r1, r1, r2
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+ ; CHECK-NEXT: and r2, r2, #31
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+ ; CHECK-NEXT: lsl r12, r12, r1
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+ ; CHECK-NEXT: orr r12, r12, r3, lsr r2
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+ ; CHECK-NEXT: lsl r3, r3, #1
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+ ; CHECK-NEXT: lsl r1, r3, r1
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+ ; CHECK-NEXT: orr r1, r1, r0, lsr r2
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+ ; CHECK-NEXT: mov r0, r12
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+ ; CHECK-NEXT: bx lr
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%f = call i64 @llvm.fshr.i64 (i64 %x , i64 %x , i64 %z )
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ret i64 %f
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}
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