Skip to content

Commit 3259768

Browse files
jacquesguanjacquesguan
authored
[RISCV] Remove experimental for bf16 extensions (#97996)
They are already ratified now.
1 parent 626c7ce commit 3259768

File tree

309 files changed

+655
-658
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

309 files changed

+655
-658
lines changed

‎clang/lib/Sema/SemaRISCV.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1391,8 +1391,7 @@ void SemaRISCV::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
13911391
!FeatureMap.lookup("zvfhmin"))
13921392
Diag(Loc, diag::err_riscv_type_requires_extension, D)
13931393
<< Ty << "zvfh or zvfhmin";
1394-
else if (Info.ElementType->isBFloat16Type() &&
1395-
!FeatureMap.lookup("experimental-zvfbfmin"))
1394+
else if (Info.ElementType->isBFloat16Type() && !FeatureMap.lookup("zvfbfmin"))
13961395
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfbfmin";
13971396
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
13981397
!FeatureMap.lookup("zve32f"))

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_trunc_v.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlse16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

0 commit comments

Comments
 (0)