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[clang][CodeGen] Regenerate tests checks after 94795a3
These were missed as I didn't expect clang codegen to be updated
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+22
-24
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2 files changed

+22
-24
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‎clang/test/CodeGen/X86/avx-shuffle-builtins.c

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=x86_64-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
2-
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=i386-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
1+
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=x86_64-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X64
2+
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=i386-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86
33
// FIXME: This is testing optimized generation of shuffle instructions and should be fixed.
44

55

@@ -129,8 +129,11 @@ __m256i test_mm256_insertf128_si256_1(__m256i a, __m128i b) {
129129
// Make sure we have the correct mask for each extractf128 case.
130130

131131
__m128 test_mm256_extractf128_ps_0(__m256 a) {
132-
// CHECK-LABEL: test_mm256_extractf128_ps_0
133-
// CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
132+
// X64-LABEL: test_mm256_extractf128_ps_0
133+
// X64: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
134+
//
135+
// X86-LABEL: test_mm256_extractf128_ps_0
136+
// X86: shufflevector{{.*}}<i32 0, i32 1>
134137
return _mm256_extractf128_ps(a, 0);
135138
}
136139

@@ -142,13 +145,16 @@ __m128d test_mm256_extractf128_pd_0(__m256d a) {
142145

143146
__m128i test_mm256_extractf128_si256_0(__m256i a) {
144147
// CHECK-LABEL: test_mm256_extractf128_si256_0
145-
// CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
148+
// CHECK: shufflevector{{.*}}<i32 0, i32 1>
146149
return _mm256_extractf128_si256(a, 0);
147150
}
148151

149152
__m128 test_mm256_extractf128_ps_1(__m256 a) {
150-
// CHECK-LABEL: test_mm256_extractf128_ps_1
151-
// CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
153+
// X64-LABEL: test_mm256_extractf128_ps_1
154+
// X64: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
155+
//
156+
// X86-LABEL: test_mm256_extractf128_ps_1
157+
// X86: shufflevector{{.*}}<i32 2, i32 3>
152158
return _mm256_extractf128_ps(a, 1);
153159
}
154160

@@ -160,7 +166,7 @@ __m128d test_mm256_extractf128_pd_1(__m256d a) {
160166

161167
__m128i test_mm256_extractf128_si256_1(__m256i a) {
162168
// CHECK-LABEL: test_mm256_extractf128_si256_1
163-
// CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
169+
// CHECK: shufflevector{{.*}}<i32 2, i32 3>
164170
return _mm256_extractf128_si256(a, 1);
165171
}
166172

‎clang/test/CodeGen/aarch64-neon-vcmla.c

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -167,10 +167,8 @@ float16x4_t test_vcmla_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t r
167167
}
168168

169169
// CHECK-LABEL: @test_vcmlaq_lane_f16(
170-
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
171-
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
172-
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
173-
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
170+
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
171+
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
174172
// CHECK: ret <8 x half> [[RES]]
175173
float16x8_t test_vcmlaq_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
176174
return vcmlaq_lane_f16(acc, lhs, rhs, 1);
@@ -243,10 +241,8 @@ float16x4_t test_vcmla_rot90_laneq_f16(float16x4_t acc, float16x4_t lhs, float16
243241
}
244242

245243
// CHECK-LABEL: @test_vcmlaq_rot90_lane_f16(
246-
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
247-
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
248-
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
249-
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
244+
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
245+
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
250246
// CHECK: ret <8 x half> [[RES]]
251247
float16x8_t test_vcmlaq_rot90_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
252248
return vcmlaq_rot90_lane_f16(acc, lhs, rhs, 1);
@@ -319,10 +315,8 @@ float16x4_t test_vcmla_rot180_laneq_f16(float16x4_t acc, float16x4_t lhs, float1
319315
}
320316

321317
// CHECK-LABEL: @test_vcmlaq_rot180_lane_f16(
322-
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
323-
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
324-
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
325-
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
318+
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
319+
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
326320
// CHECK: ret <8 x half> [[RES]]
327321
float16x8_t test_vcmlaq_rot180_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
328322
return vcmlaq_rot180_lane_f16(acc, lhs, rhs, 1);
@@ -395,10 +389,8 @@ float16x4_t test_vcmla_rot270_laneq_f16(float16x4_t acc, float16x4_t lhs, float1
395389
}
396390

397391
// CHECK-LABEL: @test_vcmlaq_rot270_lane_f16(
398-
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
399-
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
400-
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
401-
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
392+
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
393+
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
402394
// CHECK: ret <8 x half> [[RES]]
403395
float16x8_t test_vcmlaq_rot270_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
404396
return vcmlaq_rot270_lane_f16(acc, lhs, rhs, 1);

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