Skip to content

Commit 3317c9c

Browse files
nikicnikic
authored
[AMDGPU] Use getSignedConstant() where necessary (#117328)
Create signed constant using getSignedConstant(), to avoid future assertion failures when we disable implicit truncation in getConstant(). This also touches some generic legalization code, which apparently only AMDGPU tests.
1 parent 815a1bb commit 3317c9c

File tree

7 files changed

+52
-43
lines changed

7 files changed

+52
-43
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2330,10 +2330,10 @@ SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
23302330
const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
23312331
const int Precision = APFloat::semanticsPrecision(FltSem);
23322332

2333-
const SDValue MaxExp = DAG.getConstant(MaxExpVal, dl, ExpVT);
2334-
const SDValue MinExp = DAG.getConstant(MinExpVal, dl, ExpVT);
2333+
const SDValue MaxExp = DAG.getSignedConstant(MaxExpVal, dl, ExpVT);
2334+
const SDValue MinExp = DAG.getSignedConstant(MinExpVal, dl, ExpVT);
23352335

2336-
const SDValue DoubleMaxExp = DAG.getConstant(2 * MaxExpVal, dl, ExpVT);
2336+
const SDValue DoubleMaxExp = DAG.getSignedConstant(2 * MaxExpVal, dl, ExpVT);
23372337

23382338
const APFloat One(FltSem, "1.0");
23392339
APFloat ScaleUpK = scalbn(One, MaxExpVal, APFloat::rmNearestTiesToEven);
@@ -2375,7 +2375,7 @@ SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
23752375
SDValue IncN0 = DAG.getNode(ISD::ADD, dl, ExpVT, N, Increment0, NUW_NSW);
23762376

23772377
SDValue ClampMinVal =
2378-
DAG.getConstant(3 * MinExpVal + 2 * Precision, dl, ExpVT);
2378+
DAG.getSignedConstant(3 * MinExpVal + 2 * Precision, dl, ExpVT);
23792379
SDValue ClampN_Small = DAG.getNode(ISD::SMAX, dl, ExpVT, N, ClampMinVal);
23802380
SDValue IncN1 =
23812381
DAG.getNode(ISD::ADD, dl, ExpVT, ClampN_Small, Increment1, NSW);
@@ -2385,8 +2385,8 @@ SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
23852385
SDValue ScaleDown1 = DAG.getNode(ISD::FMUL, dl, VT, ScaleDown0, ScaleDownVal);
23862386

23872387
SDValue ScaleDownTwice = DAG.getSetCC(
2388-
dl, SetCCVT, N, DAG.getConstant(2 * MinExpVal + Precision, dl, ExpVT),
2389-
ISD::SETULT);
2388+
dl, SetCCVT, N,
2389+
DAG.getSignedConstant(2 * MinExpVal + Precision, dl, ExpVT), ISD::SETULT);
23902390

23912391
SDValue SelectN_Small =
23922392
DAG.getNode(ISD::SELECT, dl, ExpVT, ScaleDownTwice, IncN1, IncN0);

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,8 @@ SDNode *AMDGPUDAGToDAGISel::glueCopyToM0LDSInit(SDNode *N) const {
408408
unsigned AS = cast<MemSDNode>(N)->getAddressSpace();
409409
if (AS == AMDGPUAS::LOCAL_ADDRESS) {
410410
if (Subtarget->ldsRequiresM0Init())
411-
return glueCopyToM0(N, CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
411+
return glueCopyToM0(
412+
N, CurDAG->getSignedTargetConstant(-1, SDLoc(N), MVT::i32));
412413
} else if (AS == AMDGPUAS::REGION_ADDRESS) {
413414
MachineFunction &MF = CurDAG->getMachineFunction();
414415
unsigned Value = MF.getInfo<SIMachineFunctionInfo>()->getGDSSize();
@@ -1724,7 +1725,7 @@ bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl(SDNode *N, SDValue Addr,
17241725
}
17251726

17261727
VAddr = Addr;
1727-
Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i32);
1728+
Offset = CurDAG->getSignedTargetConstant(OffsetVal, SDLoc(), MVT::i32);
17281729
return true;
17291730
}
17301731

@@ -1832,7 +1833,7 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
18321833
}
18331834

18341835
if (SAddr) {
1835-
Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i32);
1836+
Offset = CurDAG->getSignedTargetConstant(ImmOffset, SDLoc(), MVT::i32);
18361837
return true;
18371838
}
18381839
}
@@ -1848,7 +1849,7 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
18481849
CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, SDLoc(Addr), MVT::i32,
18491850
CurDAG->getTargetConstant(0, SDLoc(), MVT::i32));
18501851
VOffset = SDValue(VMov, 0);
1851-
Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i32);
1852+
Offset = CurDAG->getSignedTargetConstant(ImmOffset, SDLoc(), MVT::i32);
18521853
return true;
18531854
}
18541855

@@ -1903,13 +1904,13 @@ bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode *Parent, SDValue Addr,
19031904
SDValue AddOffset =
19041905
SAddr.getOpcode() == ISD::TargetFrameIndex
19051906
? getMaterializedScalarImm32(Lo_32(RemainderOffset), DL)
1906-
: CurDAG->getTargetConstant(RemainderOffset, DL, MVT::i32);
1907+
: CurDAG->getSignedTargetConstant(RemainderOffset, DL, MVT::i32);
19071908
SAddr = SDValue(CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL, MVT::i32,
19081909
SAddr, AddOffset),
19091910
0);
19101911
}
19111912

1912-
Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i32);
1913+
Offset = CurDAG->getSignedTargetConstant(COffsetVal, DL, MVT::i32);
19131914

19141915
return true;
19151916
}
@@ -2058,7 +2059,7 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
20582059
std::optional<int64_t> EncodedOffset = AMDGPU::getSMRDEncodedOffset(
20592060
*Subtarget, ByteOffset, IsBuffer, HasSOffset);
20602061
if (EncodedOffset && Offset && !Imm32Only) {
2061-
*Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
2062+
*Offset = CurDAG->getSignedTargetConstant(*EncodedOffset, SL, MVT::i32);
20622063
return true;
20632064
}
20642065

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2333,7 +2333,7 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
23332333
SDValue RHS = Op.getOperand(1);
23342334

23352335
SDValue Zero = DAG.getConstant(0, DL, VT);
2336-
SDValue NegOne = DAG.getConstant(-1, DL, VT);
2336+
SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
23372337

23382338
if (VT == MVT::i32) {
23392339
if (SDValue Res = LowerDIVREM24(Op, DAG, true))
@@ -3794,7 +3794,11 @@ static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
37943794
if (Width + Offset < 32) {
37953795
uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
37963796
IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
3797-
return DAG.getConstant(Result, DL, MVT::i32);
3797+
if constexpr (std::is_signed_v<IntTy>) {
3798+
return DAG.getSignedConstant(Result, DL, MVT::i32);
3799+
} else {
3800+
return DAG.getConstant(Result, DL, MVT::i32);
3801+
}
37983802
}
37993803

38003804
return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);

‎llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -919,7 +919,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
919919
HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
920920
HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
921921
} else if (CompareVT == MVT::i32) {
922-
HWTrue = DAG.getConstant(-1, DL, CompareVT);
922+
HWTrue = DAG.getAllOnesConstant(DL, CompareVT);
923923
HWFalse = DAG.getConstant(0, DL, CompareVT);
924924
}
925925
else {
@@ -949,7 +949,7 @@ SDValue R600TargetLowering::lowerADDRSPACECAST(SDValue Op,
949949
unsigned DestAS = ASC->getDestAddressSpace();
950950

951951
if (isNullConstant(Op.getOperand(0)) && SrcAS == AMDGPUAS::FLAT_ADDRESS)
952-
return DAG.getConstant(TM.getNullPointerValue(DestAS), SL, VT);
952+
return DAG.getSignedConstant(TM.getNullPointerValue(DestAS), SL, VT);
953953

954954
return Op;
955955
}
@@ -1750,11 +1750,11 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
17501750
}
17511751

17521752
return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
1753-
SelectCC.getOperand(0), // LHS
1754-
SelectCC.getOperand(1), // RHS
1755-
DAG.getConstant(-1, DL, MVT::i32), // True
1756-
DAG.getConstant(0, DL, MVT::i32), // False
1757-
SelectCC.getOperand(4)); // CC
1753+
SelectCC.getOperand(0), // LHS
1754+
SelectCC.getOperand(1), // RHS
1755+
DAG.getAllOnesConstant(DL, MVT::i32), // True
1756+
DAG.getConstant(0, DL, MVT::i32), // False
1757+
SelectCC.getOperand(4)); // CC
17581758
}
17591759

17601760
// insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -4019,10 +4019,11 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
40194019
Align StackAlign = TFL->getStackAlign();
40204020
Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
40214021
if (Alignment && *Alignment > StackAlign) {
4022-
Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
4023-
DAG.getConstant(-(uint64_t)Alignment->value()
4024-
<< Subtarget->getWavefrontSizeLog2(),
4025-
dl, VT));
4022+
Tmp1 = DAG.getNode(
4023+
ISD::AND, dl, VT, Tmp1,
4024+
DAG.getSignedConstant(-(uint64_t)Alignment->value()
4025+
<< Subtarget->getWavefrontSizeLog2(),
4026+
dl, VT));
40264027
}
40274028

40284029
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
@@ -6771,10 +6772,10 @@ SDValue SITargetLowering::lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const {
67716772
// TODO: This should be a generic narrowing legalization, and can easily be
67726773
// for GlobalISel.
67736774

6774-
SDValue MinExp = DAG.getConstant(minIntN(16), DL, ExpVT);
6775+
SDValue MinExp = DAG.getSignedConstant(minIntN(16), DL, ExpVT);
67756776
SDValue ClampMin = DAG.getNode(ISD::SMAX, DL, ExpVT, Exp, MinExp);
67766777

6777-
SDValue MaxExp = DAG.getConstant(maxIntN(16), DL, ExpVT);
6778+
SDValue MaxExp = DAG.getSignedConstant(maxIntN(16), DL, ExpVT);
67786779
SDValue Clamp = DAG.getNode(ISD::SMIN, DL, ExpVT, ClampMin, MaxExp);
67796780

67806781
SDValue TruncExp = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Clamp);
@@ -7542,11 +7543,11 @@ SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
75427543

75437544
SDValue Vec0 = SVN->getOperand(VecIdx0);
75447545
SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec0,
7545-
DAG.getConstant(EltIdx0, SL, MVT::i32));
7546+
DAG.getSignedConstant(EltIdx0, SL, MVT::i32));
75467547

75477548
SDValue Vec1 = SVN->getOperand(VecIdx1);
75487549
SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec1,
7549-
DAG.getConstant(EltIdx1, SL, MVT::i32));
7550+
DAG.getSignedConstant(EltIdx1, SL, MVT::i32));
75507551
Pieces.push_back(DAG.getBuildVector(PackVT, SL, {Elt0, Elt1}));
75517552
}
75527553
}
@@ -9618,7 +9619,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
96189619
// On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait
96199620
if (ST.hasSplitBarriers()) {
96209621
SDValue K =
9621-
DAG.getTargetConstant(AMDGPU::Barrier::WORKGROUP, DL, MVT::i32);
9622+
DAG.getSignedTargetConstant(AMDGPU::Barrier::WORKGROUP, DL, MVT::i32);
96229623
SDValue BarSignal =
96239624
SDValue(DAG.getMachineNode(AMDGPU::S_BARRIER_SIGNAL_IMM, DL,
96249625
MVT::Other, K, Op.getOperand(0)),
@@ -11173,8 +11174,9 @@ SDValue SITargetLowering::lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const {
1117311174
SqrtS = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, SqrtID, SqrtX, Flags);
1117411175

1117511176
SDValue SqrtSAsInt = DAG.getNode(ISD::BITCAST, DL, MVT::i32, SqrtS);
11176-
SDValue SqrtSNextDownInt = DAG.getNode(ISD::ADD, DL, MVT::i32, SqrtSAsInt,
11177-
DAG.getConstant(-1, DL, MVT::i32));
11177+
SDValue SqrtSNextDownInt =
11178+
DAG.getNode(ISD::ADD, DL, MVT::i32, SqrtSAsInt,
11179+
DAG.getAllOnesConstant(DL, MVT::i32));
1117811180
SDValue SqrtSNextDown = DAG.getNode(ISD::BITCAST, DL, VT, SqrtSNextDownInt);
1117911181

1118011182
SDValue NegSqrtSNextDown =
@@ -11296,7 +11298,7 @@ SDValue SITargetLowering::lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const {
1129611298

1129711299
SDValue SqrtRet = DAG.getNode(ISD::FMA, DL, MVT::f64, SqrtD1, SqrtH1, SqrtS2);
1129811300

11299-
SDValue ScaleDownFactor = DAG.getConstant(-128, DL, MVT::i32);
11301+
SDValue ScaleDownFactor = DAG.getSignedConstant(-128, DL, MVT::i32);
1130011302
SDValue ScaleDown =
1130111303
DAG.getNode(ISD::SELECT, DL, MVT::i32, Scaling, ScaleDownFactor, ZeroInt);
1130211304
SqrtRet = DAG.getNode(ISD::FLDEXP, DL, MVT::f64, SqrtRet, ScaleDown, Flags);
@@ -14689,7 +14691,7 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1468914691
(CRHS->isZero() &&
1469014692
(CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
1469114693
return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
14692-
DAG.getConstant(-1, SL, MVT::i1));
14694+
DAG.getAllOnesConstant(SL, MVT::i1));
1469314695
if ((CRHS->isAllOnes() &&
1469414696
(CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
1469514697
(CRHS->isZero() &&
@@ -14715,7 +14717,7 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1471514717
if ((CF == CRHSVal && CC == ISD::SETEQ) ||
1471614718
(CT == CRHSVal && CC == ISD::SETNE))
1471714719
return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
14718-
DAG.getConstant(-1, SL, MVT::i1));
14720+
DAG.getAllOnesConstant(SL, MVT::i1));
1471914721
if ((CF == CRHSVal && CC == ISD::SETNE) ||
1472014722
(CT == CRHSVal && CC == ISD::SETEQ))
1472114723
return LHS.getOperand(0);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -816,27 +816,29 @@ def as_i8imm : SDNodeXForm<imm, [{
816816
}]>;
817817

818818
def as_i8timm : SDNodeXForm<timm, [{
819-
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
819+
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
820820
}]>;
821821

822822
def as_i16imm : SDNodeXForm<imm, [{
823-
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
823+
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
824824
}]>;
825825

826826
def as_i16timm : SDNodeXForm<timm, [{
827-
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
827+
// Explicit cast, as this is used with both signed and unsigned immediates.
828+
return CurDAG->getSignedTargetConstant(int16_t(N->getSExtValue()), SDLoc(N),
829+
MVT::i16);
828830
}]>;
829831

830832
def as_i32imm: SDNodeXForm<imm, [{
831-
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
833+
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
832834
}]>;
833835

834836
def as_i32timm: SDNodeXForm<timm, [{
835-
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
837+
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
836838
}]>;
837839

838840
def as_i64imm: SDNodeXForm<imm, [{
839-
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
841+
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
840842
}]>;
841843

842844
def cond_as_i32imm: SDNodeXForm<cond, [{

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3727,7 +3727,7 @@ def FPPow2ToExponentXForm : SDNodeXForm<fpimm, [{
37273727
const auto &APF = N->getValueAPF();
37283728
int Log2 = APF.getExactLog2Abs();
37293729
assert(Log2 != INT_MIN);
3730-
return CurDAG->getTargetConstant(Log2, SDLoc(N), MVT::i32);
3730+
return CurDAG->getSignedTargetConstant(Log2, SDLoc(N), MVT::i32);
37313731
}]>;
37323732

37333733
// Check if a floating point value is a power of 2 floating-point

0 commit comments

Comments
 (0)