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Revert "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
This reverts commit 657d20d. A correctness problem was reported against the review and the fix warrants re-review.
1 parent 878e590 commit 3331469

21 files changed

+510
-268
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 0 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -85,18 +85,6 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
8585
}
8686
}
8787

88-
static bool isVSlideInstr(const MachineInstr &MI) {
89-
switch (getRVVMCOpcode(MI.getOpcode())) {
90-
default:
91-
return false;
92-
case RISCV::VSLIDEDOWN_VX:
93-
case RISCV::VSLIDEDOWN_VI:
94-
case RISCV::VSLIDEUP_VX:
95-
case RISCV::VSLIDEUP_VI:
96-
return true;
97-
}
98-
}
99-
10088
/// Get the EEW for a load or store instruction. Return std::nullopt if MI is
10189
/// not a load or store which ignores SEW.
10290
static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
@@ -830,11 +818,6 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
830818
.addImm(Info.encodeVTYPE());
831819
}
832820

833-
static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) {
834-
auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL);
835-
return Fractional || LMul == 1;
836-
}
837-
838821
/// Return true if a VSETVLI is required to transition from CurInfo to Require
839822
/// before MI.
840823
bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
@@ -862,27 +845,6 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
862845
}
863846
}
864847

865-
// A slidedown/slideup with a VL of 1 whose destination is an IMPLICIT_DEF
866-
// can use any VL/SEW combination which writes at least the first element.
867-
// Notes:
868-
// * VL=1 is special only because we have existing support for zero vs
869-
// non-zero VL. We could generalize this if we had a VL > C predicate.
870-
// * The LMUL1 restriction is for machines whose latency may depend on VL.
871-
// * As above, this is only legal for IMPLICIT_DEF, not TA.
872-
if (isVSlideInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
873-
isLMUL1OrSmaller(CurInfo.getVLMUL())) {
874-
auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg());
875-
if (VRegDef && VRegDef->isImplicitDef() &&
876-
CurInfo.getSEW() >= Require.getSEW()) {
877-
Used.VLAny = false;
878-
Used.VLZeroness = true;
879-
Used.SEW = false;
880-
Used.LMUL = false;
881-
Used.SEWLMULRatio = false;
882-
Used.TailPolicy = false;
883-
}
884-
}
885-
886848
if (CurInfo.isCompatible(Used, Require))
887849
return false;
888850

‎llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ define i1 @extractelt_nxv1i1(<vscale x 1 x i8>* %x, i64 %idx) nounwind {
1010
; CHECK-NEXT: vmseq.vi v0, v8, 0
1111
; CHECK-NEXT: vmv.v.i v8, 0
1212
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
13+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
1314
; CHECK-NEXT: vslidedown.vx v8, v8, a1
1415
; CHECK-NEXT: vmv.x.s a0, v8
1516
; CHECK-NEXT: ret
@@ -27,6 +28,7 @@ define i1 @extractelt_nxv2i1(<vscale x 2 x i8>* %x, i64 %idx) nounwind {
2728
; CHECK-NEXT: vmseq.vi v0, v8, 0
2829
; CHECK-NEXT: vmv.v.i v8, 0
2930
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
31+
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
3032
; CHECK-NEXT: vslidedown.vx v8, v8, a1
3133
; CHECK-NEXT: vmv.x.s a0, v8
3234
; CHECK-NEXT: ret
@@ -44,6 +46,7 @@ define i1 @extractelt_nxv4i1(<vscale x 4 x i8>* %x, i64 %idx) nounwind {
4446
; CHECK-NEXT: vmseq.vi v0, v8, 0
4547
; CHECK-NEXT: vmv.v.i v8, 0
4648
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
49+
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
4750
; CHECK-NEXT: vslidedown.vx v8, v8, a1
4851
; CHECK-NEXT: vmv.x.s a0, v8
4952
; CHECK-NEXT: ret
@@ -61,6 +64,7 @@ define i1 @extractelt_nxv8i1(<vscale x 8 x i8>* %x, i64 %idx) nounwind {
6164
; CHECK-NEXT: vmseq.vi v0, v8, 0
6265
; CHECK-NEXT: vmv.v.i v8, 0
6366
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
67+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
6468
; CHECK-NEXT: vslidedown.vx v8, v8, a1
6569
; CHECK-NEXT: vmv.x.s a0, v8
6670
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,9 @@ define <2 x i1> @reverse_v2i1(<2 x i1> %a) {
1616
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
1717
; CHECK-NEXT: vmv.v.i v8, 0
1818
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
19+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
1920
; CHECK-NEXT: vslidedown.vi v9, v8, 1
21+
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
2022
; CHECK-NEXT: vslideup.vi v9, v8, 1
2123
; CHECK-NEXT: vmsne.vi v0, v9, 0
2224
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,9 +59,9 @@ define void @abs_v6i16(ptr %x) {
5959
; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v9
6060
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
6161
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
62+
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
6263
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
6364
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
64-
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
6565
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
6666
; LMULMAX1-RV64-NEXT: ret
6767
%a = load <6 x i16>, ptr %x

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ define i1 @extractelt_v2i1(ptr %x, i64 %idx) nounwind {
3030
; CHECK-NEXT: vmseq.vi v0, v8, 0
3131
; CHECK-NEXT: vmv.v.i v8, 0
3232
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
33+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
3334
; CHECK-NEXT: vslidedown.vx v8, v8, a1
3435
; CHECK-NEXT: vmv.x.s a0, v8
3536
; CHECK-NEXT: ret
@@ -47,6 +48,7 @@ define i1 @extractelt_v4i1(ptr %x, i64 %idx) nounwind {
4748
; CHECK-NEXT: vmseq.vi v0, v8, 0
4849
; CHECK-NEXT: vmv.v.i v8, 0
4950
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
51+
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
5052
; CHECK-NEXT: vslidedown.vx v8, v8, a1
5153
; CHECK-NEXT: vmv.x.s a0, v8
5254
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -248,6 +248,7 @@ define void @extract_v8i1_v64i1_8(ptr %x, ptr %y) {
248248
; LMULMAX1: # %bb.0:
249249
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
250250
; LMULMAX1-NEXT: vlm.v v8, (a0)
251+
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
251252
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 1
252253
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
253254
; LMULMAX1-NEXT: vsm.v v8, (a1)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

Lines changed: 27 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ define i8 @extractelt_v16i8(ptr %x) nounwind {
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1111
; CHECK-NEXT: vle8.v v8, (a0)
12+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1213
; CHECK-NEXT: vslidedown.vi v8, v8, 7
1314
; CHECK-NEXT: vmv.x.s a0, v8
1415
; CHECK-NEXT: ret
@@ -22,6 +23,7 @@ define i16 @extractelt_v8i16(ptr %x) nounwind {
2223
; CHECK: # %bb.0:
2324
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
2425
; CHECK-NEXT: vle16.v v8, (a0)
26+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
2527
; CHECK-NEXT: vslidedown.vi v8, v8, 7
2628
; CHECK-NEXT: vmv.x.s a0, v8
2729
; CHECK-NEXT: ret
@@ -35,6 +37,7 @@ define i32 @extractelt_v4i32(ptr %x) nounwind {
3537
; CHECK: # %bb.0:
3638
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
3739
; CHECK-NEXT: vle32.v v8, (a0)
40+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
3841
; CHECK-NEXT: vslidedown.vi v8, v8, 2
3942
; CHECK-NEXT: vmv.x.s a0, v8
4043
; CHECK-NEXT: ret
@@ -71,6 +74,7 @@ define half @extractelt_v8f16(ptr %x) nounwind {
7174
; CHECK: # %bb.0:
7275
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
7376
; CHECK-NEXT: vle16.v v8, (a0)
77+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
7478
; CHECK-NEXT: vslidedown.vi v8, v8, 7
7579
; CHECK-NEXT: vfmv.f.s fa0, v8
7680
; CHECK-NEXT: ret
@@ -84,6 +88,7 @@ define float @extractelt_v4f32(ptr %x) nounwind {
8488
; CHECK: # %bb.0:
8589
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
8690
; CHECK-NEXT: vle32.v v8, (a0)
91+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
8792
; CHECK-NEXT: vslidedown.vi v8, v8, 2
8893
; CHECK-NEXT: vfmv.f.s fa0, v8
8994
; CHECK-NEXT: ret
@@ -247,6 +252,7 @@ define i8 @extractelt_v16i8_idx(ptr %x, i32 zeroext %idx) nounwind {
247252
; CHECK: # %bb.0:
248253
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
249254
; CHECK-NEXT: vle8.v v8, (a0)
255+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
250256
; CHECK-NEXT: vslidedown.vx v8, v8, a1
251257
; CHECK-NEXT: vmv.x.s a0, v8
252258
; CHECK-NEXT: ret
@@ -260,6 +266,7 @@ define i16 @extractelt_v8i16_idx(ptr %x, i32 zeroext %idx) nounwind {
260266
; CHECK: # %bb.0:
261267
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
262268
; CHECK-NEXT: vle16.v v8, (a0)
269+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
263270
; CHECK-NEXT: vslidedown.vx v8, v8, a1
264271
; CHECK-NEXT: vmv.x.s a0, v8
265272
; CHECK-NEXT: ret
@@ -274,6 +281,7 @@ define i32 @extractelt_v4i32_idx(ptr %x, i32 zeroext %idx) nounwind {
274281
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
275282
; CHECK-NEXT: vle32.v v8, (a0)
276283
; CHECK-NEXT: vadd.vv v8, v8, v8
284+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
277285
; CHECK-NEXT: vslidedown.vx v8, v8, a1
278286
; CHECK-NEXT: vmv.x.s a0, v8
279287
; CHECK-NEXT: ret
@@ -289,10 +297,10 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
289297
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
290298
; RV32-NEXT: vle64.v v8, (a0)
291299
; RV32-NEXT: vadd.vv v8, v8, v8
300+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
292301
; RV32-NEXT: vslidedown.vx v8, v8, a1
293302
; RV32-NEXT: vmv.x.s a0, v8
294303
; RV32-NEXT: li a1, 32
295-
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
296304
; RV32-NEXT: vsrl.vx v8, v8, a1
297305
; RV32-NEXT: vmv.x.s a1, v8
298306
; RV32-NEXT: ret
@@ -302,6 +310,7 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
302310
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
303311
; RV64-NEXT: vle64.v v8, (a0)
304312
; RV64-NEXT: vadd.vv v8, v8, v8
313+
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
305314
; RV64-NEXT: vslidedown.vx v8, v8, a1
306315
; RV64-NEXT: vmv.x.s a0, v8
307316
; RV64-NEXT: ret
@@ -317,6 +326,7 @@ define half @extractelt_v8f16_idx(ptr %x, i32 zeroext %idx) nounwind {
317326
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
318327
; CHECK-NEXT: vle16.v v8, (a0)
319328
; CHECK-NEXT: vfadd.vv v8, v8, v8
329+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
320330
; CHECK-NEXT: vslidedown.vx v8, v8, a1
321331
; CHECK-NEXT: vfmv.f.s fa0, v8
322332
; CHECK-NEXT: ret
@@ -332,6 +342,7 @@ define float @extractelt_v4f32_idx(ptr %x, i32 zeroext %idx) nounwind {
332342
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
333343
; CHECK-NEXT: vle32.v v8, (a0)
334344
; CHECK-NEXT: vfadd.vv v8, v8, v8
345+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
335346
; CHECK-NEXT: vslidedown.vx v8, v8, a1
336347
; CHECK-NEXT: vfmv.f.s fa0, v8
337348
; CHECK-NEXT: ret
@@ -347,6 +358,7 @@ define double @extractelt_v2f64_idx(ptr %x, i32 zeroext %idx) nounwind {
347358
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
348359
; CHECK-NEXT: vle64.v v8, (a0)
349360
; CHECK-NEXT: vfadd.vv v8, v8, v8
361+
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
350362
; CHECK-NEXT: vslidedown.vx v8, v8, a1
351363
; CHECK-NEXT: vfmv.f.s fa0, v8
352364
; CHECK-NEXT: ret
@@ -517,8 +529,8 @@ define void @store_extractelt_v16i8(ptr %x, ptr %p) nounwind {
517529
; CHECK: # %bb.0:
518530
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
519531
; CHECK-NEXT: vle8.v v8, (a0)
520-
; CHECK-NEXT: vslidedown.vi v8, v8, 7
521532
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
533+
; CHECK-NEXT: vslidedown.vi v8, v8, 7
522534
; CHECK-NEXT: vse8.v v8, (a1)
523535
; CHECK-NEXT: ret
524536
%a = load <16 x i8>, ptr %x
@@ -532,8 +544,8 @@ define void @store_extractelt_v8i16(ptr %x, ptr %p) nounwind {
532544
; CHECK: # %bb.0:
533545
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
534546
; CHECK-NEXT: vle16.v v8, (a0)
535-
; CHECK-NEXT: vslidedown.vi v8, v8, 7
536547
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
548+
; CHECK-NEXT: vslidedown.vi v8, v8, 7
537549
; CHECK-NEXT: vse16.v v8, (a1)
538550
; CHECK-NEXT: ret
539551
%a = load <8 x i16>, ptr %x
@@ -547,8 +559,8 @@ define void @store_extractelt_v4i32(ptr %x, ptr %p) nounwind {
547559
; CHECK: # %bb.0:
548560
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
549561
; CHECK-NEXT: vle32.v v8, (a0)
550-
; CHECK-NEXT: vslidedown.vi v8, v8, 2
551562
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
563+
; CHECK-NEXT: vslidedown.vi v8, v8, 2
552564
; CHECK-NEXT: vse32.v v8, (a1)
553565
; CHECK-NEXT: ret
554566
%a = load <4 x i32>, ptr %x
@@ -563,9 +575,9 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
563575
; RV32: # %bb.0:
564576
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
565577
; RV32-NEXT: vle64.v v8, (a0)
578+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
566579
; RV32-NEXT: vslidedown.vi v8, v8, 1
567580
; RV32-NEXT: li a0, 32
568-
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
569581
; RV32-NEXT: vsrl.vx v9, v8, a0
570582
; RV32-NEXT: vmv.x.s a0, v9
571583
; RV32-NEXT: vmv.x.s a2, v8
@@ -577,8 +589,8 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
577589
; RV64: # %bb.0:
578590
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
579591
; RV64-NEXT: vle64.v v8, (a0)
580-
; RV64-NEXT: vslidedown.vi v8, v8, 1
581592
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
593+
; RV64-NEXT: vslidedown.vi v8, v8, 1
582594
; RV64-NEXT: vse64.v v8, (a1)
583595
; RV64-NEXT: ret
584596
%a = load <2 x i64>, ptr %x
@@ -592,8 +604,8 @@ define void @store_extractelt_v2f64(ptr %x, ptr %p) nounwind {
592604
; CHECK: # %bb.0:
593605
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
594606
; CHECK-NEXT: vle64.v v8, (a0)
595-
; CHECK-NEXT: vslidedown.vi v8, v8, 1
596607
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
608+
; CHECK-NEXT: vslidedown.vi v8, v8, 1
597609
; CHECK-NEXT: vse64.v v8, (a1)
598610
; CHECK-NEXT: ret
599611
%a = load <2 x double>, ptr %x
@@ -615,6 +627,7 @@ define i32 @extractelt_add_v4i32(<4 x i32> %x) {
615627
; RV64: # %bb.0:
616628
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
617629
; RV64-NEXT: vadd.vi v8, v8, 13
630+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
618631
; RV64-NEXT: vslidedown.vi v8, v8, 2
619632
; RV64-NEXT: vmv.x.s a0, v8
620633
; RV64-NEXT: ret
@@ -637,6 +650,7 @@ define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
637650
; RV64: # %bb.0:
638651
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
639652
; RV64-NEXT: vrsub.vi v8, v8, 13
653+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
640654
; RV64-NEXT: vslidedown.vi v8, v8, 2
641655
; RV64-NEXT: vmv.x.s a0, v8
642656
; RV64-NEXT: ret
@@ -651,6 +665,7 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
651665
; RV32NOM-NEXT: li a0, 13
652666
; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
653667
; RV32NOM-NEXT: vmul.vx v8, v8, a0
668+
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
654669
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
655670
; RV32NOM-NEXT: vmv.x.s a0, v8
656671
; RV32NOM-NEXT: ret
@@ -669,6 +684,7 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
669684
; RV64-NEXT: li a0, 13
670685
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
671686
; RV64-NEXT: vmul.vx v8, v8, a0
687+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
672688
; RV64-NEXT: vslidedown.vi v8, v8, 2
673689
; RV64-NEXT: vmv.x.s a0, v8
674690
; RV64-NEXT: ret
@@ -696,6 +712,7 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
696712
; RV32NOM-NEXT: vsra.vv v9, v8, v11
697713
; RV32NOM-NEXT: vsrl.vi v8, v8, 31
698714
; RV32NOM-NEXT: vadd.vv v8, v9, v8
715+
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
699716
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
700717
; RV32NOM-NEXT: vmv.x.s a0, v8
701718
; RV32NOM-NEXT: ret
@@ -731,6 +748,7 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
731748
; RV64-NEXT: vsra.vv v8, v8, v11
732749
; RV64-NEXT: vsrl.vi v9, v8, 31
733750
; RV64-NEXT: vadd.vv v8, v8, v9
751+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
734752
; RV64-NEXT: vslidedown.vi v8, v8, 2
735753
; RV64-NEXT: vmv.x.s a0, v8
736754
; RV64-NEXT: ret
@@ -747,6 +765,7 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
747765
; RV32NOM-NEXT: lui a0, 322639
748766
; RV32NOM-NEXT: addi a0, a0, -945
749767
; RV32NOM-NEXT: vmulhu.vx v8, v8, a0
768+
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
750769
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
751770
; RV32NOM-NEXT: vmv.x.s a0, v8
752771
; RV32NOM-NEXT: srli a0, a0, 2
@@ -771,6 +790,7 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
771790
; RV64-NEXT: addiw a0, a0, -945
772791
; RV64-NEXT: vmulhu.vx v8, v8, a0
773792
; RV64-NEXT: vsrl.vi v8, v8, 2
793+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
774794
; RV64-NEXT: vslidedown.vi v8, v8, 2
775795
; RV64-NEXT: vmv.x.s a0, v8
776796
; RV64-NEXT: ret

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