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[NVPTX]: Fix typos
1 parent 2c23cd9 commit 34a501c

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4 files changed

+44
-39
lines changed

4 files changed

+44
-39
lines changed

‎llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -228,9 +228,9 @@ void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum,
228228
const MCOperand &MO = MI->getOperand(OpNum);
229229
int Imm = (int) MO.getImm();
230230
if (!strcmp(Modifier, "sem")) {
231-
auto ordering =
231+
auto Ordering =
232232
NVPTX::Ordering(static_cast<NVPTX::OrderingUnderlyingType>(Imm));
233-
switch (ordering) {
233+
switch (Ordering) {
234234
case NVPTX::Ordering::NotAtomic:
235235
break;
236236
case NVPTX::Ordering::Volatile:
@@ -251,15 +251,15 @@ void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum,
251251
default:
252252
SmallString<256> Msg;
253253
raw_svector_ostream OS(Msg);
254-
OS << "NVPTX LdStCode Printer does not support \"" << ordering
254+
OS << "NVPTX LdStCode Printer does not support \"" << Ordering
255255
<< "\" sem modifier.";
256256
report_fatal_error(OS.str());
257257
break;
258258
}
259259
} else if (!strcmp(Modifier, "sc")) {
260-
auto ordering =
260+
auto Ordering =
261261
NVPTX::Ordering(static_cast<NVPTX::OrderingUnderlyingType>(Imm));
262-
switch (ordering) {
262+
switch (Ordering) {
263263
// TODO: refactor fence insertion in ISelDagToDag instead of here
264264
// as part of implementing atomicrmw seq_cst.
265265
case NVPTX::Ordering::SequentiallyConsistent:

‎llvm/lib/Target/NVPTX/NVPTX.h

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -122,32 +122,32 @@ enum class Ordering : OrderingUnderlyingType {
122122
LAST = RelaxedMMIO
123123
};
124124

125-
template <typename OStream> OStream &operator<<(OStream &os, Ordering order) {
126-
switch (order) {
125+
template <typename OStream> OStream &operator<<(OStream &O, Ordering Order) {
126+
switch (Order) {
127127
case Ordering::NotAtomic:
128-
os << "NotAtomic";
129-
return os;
128+
O << "NotAtomic";
129+
return O;
130130
case Ordering::Relaxed:
131-
os << "Relaxed";
132-
return os;
131+
O << "Relaxed";
132+
return O;
133133
case Ordering::Acquire:
134-
os << "Acquire";
135-
return os;
134+
O << "Acquire";
135+
return O;
136136
case Ordering::Release:
137-
os << "Release";
138-
return os;
137+
O << "Release";
138+
return O;
139139
// case Ordering::AcquireRelease:
140-
// os << "AcquireRelease";
141-
// return os;
140+
// O << "AcquireRelease";
141+
// return O;
142142
case Ordering::SequentiallyConsistent:
143-
os << "SequentiallyConsistent";
144-
return os;
143+
O << "SequentiallyConsistent";
144+
return O;
145145
case Ordering::Volatile:
146-
os << "Volatile";
147-
return os;
146+
O << "Volatile";
147+
return O;
148148
case Ordering::RelaxedMMIO:
149-
os << "RelaxedMMIO";
150-
return os;
149+
O << "RelaxedMMIO";
150+
return O;
151151
}
152152
report_fatal_error("unknown ordering");
153153
}

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -715,12 +715,12 @@ static unsigned int getCodeAddrSpace(MemSDNode *N) {
715715
}
716716

717717
struct OperationOrderings {
718-
NVPTX::OrderingUnderlyingType instr_ordering;
719-
NVPTX::OrderingUnderlyingType fence_ordering;
718+
NVPTX::OrderingUnderlyingType InstrOrdering;
719+
NVPTX::OrderingUnderlyingType FenceOrdering;
720720
OperationOrderings(NVPTX::Ordering o = NVPTX::Ordering::NotAtomic,
721721
NVPTX::Ordering f = NVPTX::Ordering::NotAtomic)
722-
: instr_ordering(static_cast<NVPTX::OrderingUnderlyingType>(o)),
723-
fence_ordering(static_cast<NVPTX::OrderingUnderlyingType>(f)) {}
722+
: InstrOrdering(static_cast<NVPTX::OrderingUnderlyingType>(o)),
723+
FenceOrdering(static_cast<NVPTX::OrderingUnderlyingType>(f)) {}
724724
};
725725

726726
static OperationOrderings
@@ -759,12 +759,19 @@ getOperationOrderings(MemSDNode *N, const NVPTXSubtarget *Subtarget) {
759759
// Lustig et al, A Formal Analysis of the NVIDIA PTX Memory Consistency Model, ASPLOS’19.
760760
// https://dl.acm.org/doi/pdf/10.1145/3297858.3304043
761761
//
762-
// | CUDA C++ Atomic Operation or Atomic Fence | PTX Atomic Operation or Fence |
763-
// |-----------------------------------------------------------------------------|-----------------------------------------|
764-
// | cuda::atomic_thread_fence(memory_order_seq_cst, cuda::thread_scope_<scope>) | fence.sc.<scope>; |
765-
// | cuda::atomic_load(memory_order_seq_cst, cuda::thread_scope_<scope>) | fence.sc.<scope>; ld.acquire.<scope>; |
766-
// | cuda::atomic_store(memory_order_seq_cst, cuda::thread_scope_<scope>) | fence.sc.<scope>; st.release.<scope>; |
767-
// | cuda::atomic_fetch_<op>(memory_order_seq_cst, cuda::thread_scope_<scope>) | fence.sc.<scope>; atom.acq_rel.<scope>; |
762+
// | CUDA C++ Atomic Operation or Atomic Fence | PTX Atomic Operation or Fence |
763+
// |------------------------------------------------------|-------------------------------|
764+
// | cuda::atomic_thread_fence | fence.sc.<scope>; |
765+
// | (memory_order_seq_cst, cuda::thread_scope_<scope>) | |
766+
// |------------------------------------------------------|-------------------------------|
767+
// | cuda::atomic_load | fence.sc.<scope>; |
768+
// | (memory_order_seq_cst, cuda::thread_scope_<scope>) | ld.acquire.<scope>; |
769+
// |------------------------------------------------------|-------------------------------|
770+
// | cuda::atomic_store | fence.sc.<scope>; |
771+
// | (memory_order_seq_cst, cuda::thread_scope_<scope>) | st.release.<scope>; |
772+
// |------------------------------------------------------|-------------------------------|
773+
// | cuda::atomic_fetch_<op> | fence.sc.<scope>; |
774+
// | (memory_order_seq_cst, cuda::thread_scope_<scope>) | atom.acq_rel.<scope>; |
768775

769776
// clang-format on
770777

@@ -897,11 +904,11 @@ getOperationOrderings(MemSDNode *N, const NVPTXSubtarget *Subtarget) {
897904
//
898905
// This sets the ordering of the fence to SequentiallyConsistent, and
899906
// sets the corresponding ordering for the instruction.
900-
NVPTX::Ordering ord;
907+
NVPTX::Ordering InstrOrder;
901908
if (N->readMem()) {
902-
ord = NVPTX::Ordering::Acquire;
909+
InstrOrder = NVPTX::Ordering::Acquire;
903910
} else if (N->writeMem()) {
904-
ord = NVPTX::Ordering::Release;
911+
InstrOrder = NVPTX::Ordering::Release;
905912
} else {
906913
SmallString<256> Msg;
907914
raw_svector_ostream OS(Msg);
@@ -912,7 +919,7 @@ getOperationOrderings(MemSDNode *N, const NVPTXSubtarget *Subtarget) {
912919
report_fatal_error(OS.str());
913920
}
914921
return AddrGenericOrGlobalOrShared
915-
? OperationOrderings(ord,
922+
? OperationOrderings(InstrOrder,
916923
NVPTX::Ordering::SequentiallyConsistent)
917924
: OperationOrderings(NVPTX::Ordering::NotAtomic);
918925
}

‎llvm/test/CodeGen/NVPTX/load-store-sm-70.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1330,5 +1330,3 @@ define void @local_acq_rel_volatile(ptr addrspace(5) %a, ptr addrspace(5) %b, pt
13301330

13311331
ret void
13321332
}
1333-
1334-

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