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Pavel Kosov
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[SchedModels][CortexA55] Fix scheduling of FP loads
Patch fixes scheduling of FP load instructions with pre/post increment adding WriteAdr for address operand. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D116361 OS Laboratory. Huawei Russian Research Institute. Saint-Petersburg
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3 files changed

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-199
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‎llvm/lib/Target/AArch64/AArch64SchedA55.td

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -235,10 +235,14 @@ def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
235235
//---
236236
// Miscellaneous
237237
//---
238-
def : InstRW<[CortexA55WriteVLD1SI,CortexA55WriteLDP1], (instregex "LDPS?W")>;
239-
def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP1], (instregex "LDPS[^W]")>;
240-
def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)")>;
241-
def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP4], (instregex "LDPQ")>;
238+
def : InstRW<[CortexA55WriteVLD1SI,CortexA55WriteLDP1], (instregex "LDPS?Wi")>;
239+
def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP1], (instregex "LDPSi")>;
240+
def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)i")>;
241+
def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP4], (instregex "LDPQi")>;
242+
def : InstRW<[WriteAdr, CortexA55WriteVLD1SI,CortexA55WriteLDP1], (instregex "LDPS?W(pre|post)")>;
243+
def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP1], (instregex "LDPS(pre|post)")>;
244+
def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)(pre|post)")>;
245+
def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP4], (instregex "LDPQ(pre|post)")>;
242246
def : InstRW<[WriteI], (instrs COPY)>;
243247
//---
244248
// Vector Loads - 64-bit per cycle

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -2428,44 +2428,44 @@ drps
24282428
# CHECK-NEXT: 1 1 1.00 * stp q3, q5, [sp]
24292429
# CHECK-NEXT: 1 1 1.00 * stp q17, q19, [sp, #1008]
24302430
# CHECK-NEXT: 2 6 6.00 * ldp q23, q29, [x1, #-1024]
2431-
# CHECK-NEXT: 2 4 1.00 * ldp w3, w5, [sp], #0
2431+
# CHECK-NEXT: 3 4 1.00 * ldp w3, w5, [sp], #0
24322432
# CHECK-NEXT: 2 1 1.00 * stp wzr, w9, [sp], #252
2433-
# CHECK-NEXT: 2 4 1.00 * ldp w2, wzr, [sp], #-256
2434-
# CHECK-NEXT: 2 4 1.00 * ldp w9, w10, [sp], #4
2435-
# CHECK-NEXT: 2 4 1.00 * ldpsw x9, x10, [sp], #4
2436-
# CHECK-NEXT: 2 4 1.00 * ldpsw x9, x10, [x2], #-256
2437-
# CHECK-NEXT: 2 4 1.00 * ldpsw x20, x30, [sp], #252
2438-
# CHECK-NEXT: 2 5 2.00 * ldp x21, x29, [x2], #504
2439-
# CHECK-NEXT: 2 5 2.00 * ldp x22, x23, [x3], #-512
2440-
# CHECK-NEXT: 2 5 2.00 * ldp x24, x25, [x4], #8
2441-
# CHECK-NEXT: 2 4 1.00 * ldp s29, s28, [sp], #252
2433+
# CHECK-NEXT: 3 4 1.00 * ldp w2, wzr, [sp], #-256
2434+
# CHECK-NEXT: 3 4 1.00 * ldp w9, w10, [sp], #4
2435+
# CHECK-NEXT: 3 4 1.00 * ldpsw x9, x10, [sp], #4
2436+
# CHECK-NEXT: 3 4 1.00 * ldpsw x9, x10, [x2], #-256
2437+
# CHECK-NEXT: 3 4 1.00 * ldpsw x20, x30, [sp], #252
2438+
# CHECK-NEXT: 3 5 2.00 * ldp x21, x29, [x2], #504
2439+
# CHECK-NEXT: 3 5 2.00 * ldp x22, x23, [x3], #-512
2440+
# CHECK-NEXT: 3 5 2.00 * ldp x24, x25, [x4], #8
2441+
# CHECK-NEXT: 3 4 1.00 * ldp s29, s28, [sp], #252
24422442
# CHECK-NEXT: 2 1 1.00 * stp s27, s26, [sp], #-256
2443-
# CHECK-NEXT: 2 4 1.00 * ldp s1, s2, [x3], #44
2443+
# CHECK-NEXT: 3 4 1.00 * ldp s1, s2, [x3], #44
24442444
# CHECK-NEXT: 2 1 1.00 * stp d3, d5, [x9], #504
24452445
# CHECK-NEXT: 2 1 1.00 * stp d7, d11, [x10], #-512
2446-
# CHECK-NEXT: 2 5 2.00 * ldp d2, d3, [x30], #-8
2446+
# CHECK-NEXT: 3 5 2.00 * ldp d2, d3, [x30], #-8
24472447
# CHECK-NEXT: 2 1 1.00 * stp q3, q5, [sp], #0
24482448
# CHECK-NEXT: 2 1 1.00 * stp q17, q19, [sp], #1008
2449-
# CHECK-NEXT: 2 6 6.00 * ldp q23, q29, [x1], #-1024
2450-
# CHECK-NEXT: 2 4 1.00 * ldp w3, w5, [sp, #0]!
2449+
# CHECK-NEXT: 3 6 6.00 * ldp q23, q29, [x1], #-1024
2450+
# CHECK-NEXT: 3 4 1.00 * ldp w3, w5, [sp, #0]!
24512451
# CHECK-NEXT: 2 1 1.00 * stp wzr, w9, [sp, #252]!
2452-
# CHECK-NEXT: 2 4 1.00 * ldp w2, wzr, [sp, #-256]!
2453-
# CHECK-NEXT: 2 4 1.00 * ldp w9, w10, [sp, #4]!
2454-
# CHECK-NEXT: 2 4 1.00 * ldpsw x9, x10, [sp, #4]!
2455-
# CHECK-NEXT: 2 4 1.00 * ldpsw x9, x10, [x2, #-256]!
2456-
# CHECK-NEXT: 2 4 1.00 * ldpsw x20, x30, [sp, #252]!
2457-
# CHECK-NEXT: 2 5 2.00 * ldp x21, x29, [x2, #504]!
2458-
# CHECK-NEXT: 2 5 2.00 * ldp x22, x23, [x3, #-512]!
2459-
# CHECK-NEXT: 2 5 2.00 * ldp x24, x25, [x4, #8]!
2460-
# CHECK-NEXT: 2 4 1.00 * ldp s29, s28, [sp, #252]!
2452+
# CHECK-NEXT: 3 4 1.00 * ldp w2, wzr, [sp, #-256]!
2453+
# CHECK-NEXT: 3 4 1.00 * ldp w9, w10, [sp, #4]!
2454+
# CHECK-NEXT: 3 4 1.00 * ldpsw x9, x10, [sp, #4]!
2455+
# CHECK-NEXT: 3 4 1.00 * ldpsw x9, x10, [x2, #-256]!
2456+
# CHECK-NEXT: 3 4 1.00 * ldpsw x20, x30, [sp, #252]!
2457+
# CHECK-NEXT: 3 5 2.00 * ldp x21, x29, [x2, #504]!
2458+
# CHECK-NEXT: 3 5 2.00 * ldp x22, x23, [x3, #-512]!
2459+
# CHECK-NEXT: 3 5 2.00 * ldp x24, x25, [x4, #8]!
2460+
# CHECK-NEXT: 3 4 1.00 * ldp s29, s28, [sp, #252]!
24612461
# CHECK-NEXT: 2 1 1.00 * stp s27, s26, [sp, #-256]!
2462-
# CHECK-NEXT: 2 4 1.00 * ldp s1, s2, [x3, #44]!
2462+
# CHECK-NEXT: 3 4 1.00 * ldp s1, s2, [x3, #44]!
24632463
# CHECK-NEXT: 2 1 1.00 * stp d3, d5, [x9, #504]!
24642464
# CHECK-NEXT: 2 1 1.00 * stp d7, d11, [x10, #-512]!
2465-
# CHECK-NEXT: 2 5 2.00 * ldp d2, d3, [x30, #-8]!
2465+
# CHECK-NEXT: 3 5 2.00 * ldp d2, d3, [x30, #-8]!
24662466
# CHECK-NEXT: 2 1 1.00 * stp q3, q5, [sp, #0]!
24672467
# CHECK-NEXT: 2 1 1.00 * stp q17, q19, [sp, #1008]!
2468-
# CHECK-NEXT: 2 6 6.00 * ldp q23, q29, [x1, #-1024]!
2468+
# CHECK-NEXT: 3 6 6.00 * ldp q23, q29, [x1, #-1024]!
24692469
# CHECK-NEXT: 2 5 2.00 * ldnp w3, w5, [sp]
24702470
# CHECK-NEXT: 1 1 1.00 * stnp wzr, w9, [sp, #252]
24712471
# CHECK-NEXT: 2 5 2.00 * ldnp w2, wzr, [sp, #-256]

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