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[RISCV][GISel] Add G_SEXTLOAD to legalizer and regbank select. Add instruction selection tests.
This updates our G_SEXTLOAD support to the same level as G_ZEXTLOAD. Still missing some legalizer rules for both though.
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8 files changed

+503
-7
lines changed

8 files changed

+503
-7
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -111,14 +111,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
111111
.clampScalar(0, s32, XLenLLT)
112112
.lower();
113113

114-
auto &ZExtLoadActions = getActionDefinitionsBuilder(G_ZEXTLOAD)
115-
.legalForTypesWithMemDesc({{s32, p0, s8, 8},
116-
{s32, p0, s16, 16},
117-
{XLenLLT, p0, s8, 8},
118-
{XLenLLT, p0, s16, 16}});
114+
auto &ExtLoadActions =
115+
getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
116+
.legalForTypesWithMemDesc({{s32, p0, s8, 8},
117+
{s32, p0, s16, 16},
118+
{XLenLLT, p0, s8, 8},
119+
{XLenLLT, p0, s16, 16}});
119120
if (XLen == 64)
120-
ZExtLoadActions.legalForTypesWithMemDesc({{XLenLLT, p0, s32, 32}});
121-
ZExtLoadActions.lower();
121+
ExtLoadActions.legalForTypesWithMemDesc({{XLenLLT, p0, s32, 32}});
122+
ExtLoadActions.lower();
122123

123124
getActionDefinitionsBuilder(G_PTR_ADD)
124125
.legalFor({{p0, XLenLLT}});

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
133133
case TargetOpcode::G_SEXT:
134134
case TargetOpcode::G_ZEXT:
135135
case TargetOpcode::G_LOAD:
136+
case TargetOpcode::G_SEXTLOAD:
136137
case TargetOpcode::G_ZEXTLOAD:
137138
case TargetOpcode::G_STORE:
138139
break;

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,50 @@ body: |
110110
$x10 = COPY %1(s32)
111111
PseudoRET implicit $x10
112112
113+
...
114+
---
115+
name: sextload_i8
116+
legalized: true
117+
regBankSelected: true
118+
tracksRegLiveness: true
119+
body: |
120+
bb.0:
121+
liveins: $x10
122+
123+
; CHECK-LABEL: name: sextload_i8
124+
; CHECK: liveins: $x10
125+
; CHECK-NEXT: {{ $}}
126+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
127+
; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
128+
; CHECK-NEXT: $x10 = COPY [[LB]]
129+
; CHECK-NEXT: PseudoRET implicit $x10
130+
%0:gprb(p0) = COPY $x10
131+
%1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
132+
$x10 = COPY %1(s32)
133+
PseudoRET implicit $x10
134+
135+
...
136+
---
137+
name: sextload_i16
138+
legalized: true
139+
regBankSelected: true
140+
tracksRegLiveness: true
141+
body: |
142+
bb.0:
143+
liveins: $x10
144+
145+
; CHECK-LABEL: name: sextload_i16
146+
; CHECK: liveins: $x10
147+
; CHECK-NEXT: {{ $}}
148+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
149+
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
150+
; CHECK-NEXT: $x10 = COPY [[LH]]
151+
; CHECK-NEXT: PseudoRET implicit $x10
152+
%0:gprb(p0) = COPY $x10
153+
%1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
154+
$x10 = COPY %1(s32)
155+
PseudoRET implicit $x10
156+
113157
...
114158
---
115159
name: load_p0

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,72 @@ body: |
176176
$x10 = COPY %1(s64)
177177
PseudoRET implicit $x10
178178
179+
...
180+
---
181+
name: sextload_i8_i64
182+
legalized: true
183+
regBankSelected: true
184+
tracksRegLiveness: true
185+
body: |
186+
bb.0:
187+
liveins: $x10
188+
189+
; CHECK-LABEL: name: sextload_i8_i64
190+
; CHECK: liveins: $x10
191+
; CHECK-NEXT: {{ $}}
192+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
193+
; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
194+
; CHECK-NEXT: $x10 = COPY [[LB]]
195+
; CHECK-NEXT: PseudoRET implicit $x10
196+
%0:gprb(p0) = COPY $x10
197+
%1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
198+
$x10 = COPY %1(s64)
199+
PseudoRET implicit $x10
200+
201+
...
202+
---
203+
name: sextload_i16_i64
204+
legalized: true
205+
regBankSelected: true
206+
tracksRegLiveness: true
207+
body: |
208+
bb.0:
209+
liveins: $x10
210+
211+
; CHECK-LABEL: name: sextload_i16_i64
212+
; CHECK: liveins: $x10
213+
; CHECK-NEXT: {{ $}}
214+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
215+
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
216+
; CHECK-NEXT: $x10 = COPY [[LH]]
217+
; CHECK-NEXT: PseudoRET implicit $x10
218+
%0:gprb(p0) = COPY $x10
219+
%1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
220+
$x10 = COPY %1(s64)
221+
PseudoRET implicit $x10
222+
223+
...
224+
---
225+
name: sextload_i32_i64
226+
legalized: true
227+
regBankSelected: true
228+
tracksRegLiveness: true
229+
body: |
230+
bb.0:
231+
liveins: $x10
232+
233+
; CHECK-LABEL: name: sextload_i32_i64
234+
; CHECK: liveins: $x10
235+
; CHECK-NEXT: {{ $}}
236+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
237+
; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))
238+
; CHECK-NEXT: $x10 = COPY [[LW]]
239+
; CHECK-NEXT: PseudoRET implicit $x10
240+
%0:gprb(p0) = COPY $x10
241+
%1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
242+
$x10 = COPY %1(s64)
243+
PseudoRET implicit $x10
244+
179245
...
180246
---
181247
name: load_i8_i32

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
3+
# RUN: | FileCheck %s
4+
5+
---
6+
name: zextload_i8_i32
7+
body: |
8+
bb.0:
9+
liveins: $x10
10+
11+
; CHECK-LABEL: name: zextload_i8_i32
12+
; CHECK: liveins: $x10
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
15+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
16+
; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
17+
; CHECK-NEXT: PseudoRET implicit $x10
18+
%0:_(p0) = COPY $x10
19+
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
20+
$x10 = COPY %2(s32)
21+
PseudoRET implicit $x10
22+
23+
...
24+
---
25+
name: zextload_i16_i32
26+
body: |
27+
bb.0:
28+
liveins: $x10
29+
30+
; CHECK-LABEL: name: zextload_i16_i32
31+
; CHECK: liveins: $x10
32+
; CHECK-NEXT: {{ $}}
33+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
34+
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
35+
; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
36+
; CHECK-NEXT: PseudoRET implicit $x10
37+
%0:_(p0) = COPY $x10
38+
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
39+
$x10 = COPY %2(s32)
40+
PseudoRET implicit $x10
41+
42+
...
43+
---
44+
name: sextload_i8_i32
45+
body: |
46+
bb.0:
47+
liveins: $x10
48+
49+
; CHECK-LABEL: name: sextload_i8_i32
50+
; CHECK: liveins: $x10
51+
; CHECK-NEXT: {{ $}}
52+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
53+
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
54+
; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
55+
; CHECK-NEXT: PseudoRET implicit $x10
56+
%0:_(p0) = COPY $x10
57+
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
58+
$x10 = COPY %2(s32)
59+
PseudoRET implicit $x10
60+
61+
...
62+
---
63+
name: sextload_i16_i32
64+
body: |
65+
bb.0:
66+
liveins: $x10
67+
68+
; CHECK-LABEL: name: sextload_i16_i32
69+
; CHECK: liveins: $x10
70+
; CHECK-NEXT: {{ $}}
71+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
72+
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
73+
; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
74+
; CHECK-NEXT: PseudoRET implicit $x10
75+
%0:_(p0) = COPY $x10
76+
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
77+
$x10 = COPY %2(s32)
78+
PseudoRET implicit $x10
79+
80+
...

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