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[AMDGPU][True16][MC] true16 for v_sin_f16 (#120692)
Support true16 format for v_sin_f16 in MC
1 parent e32afde commit 34d2c3b

29 files changed

+1062
-462
lines changed

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1045,7 +1045,7 @@ defm V_CEIL_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16
10451045
defm V_TRUNC_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05d, "v_trunc_f16">;
10461046
defm V_RNDNE_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05e, "v_rndne_f16">;
10471047
defm V_FRACT_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05f, "v_fract_f16">;
1048-
defm V_SIN_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x060, "v_sin_f16">;
1048+
defm V_SIN_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x060, "v_sin_f16">;
10491049
defm V_COS_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x061, "v_cos_f16">;
10501050
defm V_SAT_PK_U8_I16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x062, "v_sat_pk_u8_i16">;
10511051
defm V_CVT_NORM_I16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;

‎llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
55
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
66
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s
7+
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX12 %s
78

89
define amdgpu_kernel void @sin_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
910
; GFX6-LABEL: sin_f16:
@@ -80,6 +81,19 @@ define amdgpu_kernel void @sin_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
8081
; GFX11-NEXT: v_sin_f16_e32 v1, v1
8182
; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
8283
; GFX11-NEXT: s_endpgm
84+
;
85+
; GFX12-LABEL: sin_f16:
86+
; GFX12: ; %bb.0:
87+
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
88+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
89+
; GFX12-NEXT: s_wait_kmcnt 0x0
90+
; GFX12-NEXT: global_load_u16 v1, v0, s[2:3]
91+
; GFX12-NEXT: s_wait_loadcnt 0x0
92+
; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1
93+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
94+
; GFX12-NEXT: v_sin_f16_e32 v1, v1
95+
; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
96+
; GFX12-NEXT: s_endpgm
8397
%a.val = load half, ptr addrspace(1) %a
8498
%r.val = call half @llvm.sin.f16(half %a.val)
8599
store half %r.val, ptr addrspace(1) %r
@@ -188,6 +202,24 @@ define amdgpu_kernel void @sin_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
188202
; GFX11-NEXT: v_pack_b32_f16 v1, v1, v2
189203
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
190204
; GFX11-NEXT: s_endpgm
205+
;
206+
; GFX12-LABEL: sin_v2f16:
207+
; GFX12: ; %bb.0:
208+
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
209+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
210+
; GFX12-NEXT: s_wait_kmcnt 0x0
211+
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
212+
; GFX12-NEXT: s_wait_loadcnt 0x0
213+
; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v1
214+
; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1
215+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
216+
; GFX12-NEXT: v_mul_f16_e32 v2, 0.15915494, v2
217+
; GFX12-NEXT: v_sin_f16_e32 v1, v1
218+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
219+
; GFX12-NEXT: v_sin_f16_e32 v2, v2
220+
; GFX12-NEXT: v_pack_b32_f16 v1, v1, v2
221+
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
222+
; GFX12-NEXT: s_endpgm
191223
%a.val = load <2 x half>, ptr addrspace(1) %a
192224
%r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val)
193225
store <2 x half> %r.val, ptr addrspace(1) %r

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1.s

Lines changed: 45 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -3305,50 +3305,65 @@ v_sat_pk_u8_i16 v5.h, src_scc
33053305
v_sat_pk_u8_i16 v127.h, 0xfe0b
33063306
// GFX11: v_sat_pk_u8_i16_e32 v127.h, 0xfe0b ; encoding: [0xff,0xc4,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
33073307

3308-
v_sin_f16 v5, v1
3309-
// GFX11: v_sin_f16_e32 v5, v1 ; encoding: [0x01,0xc1,0x0a,0x7e]
3308+
v_sin_f16 v5.l, v1.l
3309+
// GFX11: v_sin_f16_e32 v5.l, v1.l ; encoding: [0x01,0xc1,0x0a,0x7e]
33103310

3311-
v_sin_f16 v5, v127
3312-
// GFX11: v_sin_f16_e32 v5, v127 ; encoding: [0x7f,0xc1,0x0a,0x7e]
3311+
v_sin_f16 v5.l, v127.l
3312+
// GFX11: v_sin_f16_e32 v5.l, v127.l ; encoding: [0x7f,0xc1,0x0a,0x7e]
33133313

3314-
v_sin_f16 v5, s1
3315-
// GFX11: v_sin_f16_e32 v5, s1 ; encoding: [0x01,0xc0,0x0a,0x7e]
3314+
v_sin_f16 v5.l, s1
3315+
// GFX11: v_sin_f16_e32 v5.l, s1 ; encoding: [0x01,0xc0,0x0a,0x7e]
33163316

3317-
v_sin_f16 v5, s105
3318-
// GFX11: v_sin_f16_e32 v5, s105 ; encoding: [0x69,0xc0,0x0a,0x7e]
3317+
v_sin_f16 v5.l, s105
3318+
// GFX11: v_sin_f16_e32 v5.l, s105 ; encoding: [0x69,0xc0,0x0a,0x7e]
33193319

3320-
v_sin_f16 v5, vcc_lo
3321-
// GFX11: v_sin_f16_e32 v5, vcc_lo ; encoding: [0x6a,0xc0,0x0a,0x7e]
3320+
v_sin_f16 v5.l, vcc_lo
3321+
// GFX11: v_sin_f16_e32 v5.l, vcc_lo ; encoding: [0x6a,0xc0,0x0a,0x7e]
33223322

3323-
v_sin_f16 v5, vcc_hi
3324-
// GFX11: v_sin_f16_e32 v5, vcc_hi ; encoding: [0x6b,0xc0,0x0a,0x7e]
3323+
v_sin_f16 v5.l, vcc_hi
3324+
// GFX11: v_sin_f16_e32 v5.l, vcc_hi ; encoding: [0x6b,0xc0,0x0a,0x7e]
33253325

3326-
v_sin_f16 v5, ttmp15
3327-
// GFX11: v_sin_f16_e32 v5, ttmp15 ; encoding: [0x7b,0xc0,0x0a,0x7e]
3326+
v_sin_f16 v5.l, ttmp15
3327+
// GFX11: v_sin_f16_e32 v5.l, ttmp15 ; encoding: [0x7b,0xc0,0x0a,0x7e]
33283328

3329-
v_sin_f16 v5, m0
3330-
// GFX11: v_sin_f16_e32 v5, m0 ; encoding: [0x7d,0xc0,0x0a,0x7e]
3329+
v_sin_f16 v5.l, m0
3330+
// GFX11: v_sin_f16_e32 v5.l, m0 ; encoding: [0x7d,0xc0,0x0a,0x7e]
33313331

3332-
v_sin_f16 v5, exec_lo
3333-
// GFX11: v_sin_f16_e32 v5, exec_lo ; encoding: [0x7e,0xc0,0x0a,0x7e]
3332+
v_sin_f16 v5.l, exec_lo
3333+
// GFX11: v_sin_f16_e32 v5.l, exec_lo ; encoding: [0x7e,0xc0,0x0a,0x7e]
33343334

3335-
v_sin_f16 v5, exec_hi
3336-
// GFX11: v_sin_f16_e32 v5, exec_hi ; encoding: [0x7f,0xc0,0x0a,0x7e]
3335+
v_sin_f16 v5.l, exec_hi
3336+
// GFX11: v_sin_f16_e32 v5.l, exec_hi ; encoding: [0x7f,0xc0,0x0a,0x7e]
33373337

3338-
v_sin_f16 v5, null
3339-
// GFX11: v_sin_f16_e32 v5, null ; encoding: [0x7c,0xc0,0x0a,0x7e]
3338+
v_sin_f16 v5.l, null
3339+
// GFX11: v_sin_f16_e32 v5.l, null ; encoding: [0x7c,0xc0,0x0a,0x7e]
33403340

3341-
v_sin_f16 v5, -1
3342-
// GFX11: v_sin_f16_e32 v5, -1 ; encoding: [0xc1,0xc0,0x0a,0x7e]
3341+
v_sin_f16 v5.l, -1
3342+
// GFX11: v_sin_f16_e32 v5.l, -1 ; encoding: [0xc1,0xc0,0x0a,0x7e]
33433343

3344-
v_sin_f16 v5, 0.5
3345-
// GFX11: v_sin_f16_e32 v5, 0.5 ; encoding: [0xf0,0xc0,0x0a,0x7e]
3344+
v_sin_f16 v5.l, 0.5
3345+
// GFX11: v_sin_f16_e32 v5.l, 0.5 ; encoding: [0xf0,0xc0,0x0a,0x7e]
33463346

3347-
v_sin_f16 v5, src_scc
3348-
// GFX11: v_sin_f16_e32 v5, src_scc ; encoding: [0xfd,0xc0,0x0a,0x7e]
3347+
v_sin_f16 v5.l, src_scc
3348+
// GFX11: v_sin_f16_e32 v5.l, src_scc ; encoding: [0xfd,0xc0,0x0a,0x7e]
33493349

3350-
v_sin_f16 v127, 0xfe0b
3351-
// GFX11: v_sin_f16_e32 v127, 0xfe0b ; encoding: [0xff,0xc0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
3350+
v_sin_f16 v127.l, 0xfe0b
3351+
// GFX11: v_sin_f16_e32 v127.l, 0xfe0b ; encoding: [0xff,0xc0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
3352+
3353+
v_sin_f16 v5.l, v1.h
3354+
// GFX11: v_sin_f16_e32 v5.l, v1.h ; encoding: [0x81,0xc1,0x0a,0x7e]
3355+
3356+
v_sin_f16 v5.l, v127.h
3357+
// GFX11: v_sin_f16_e32 v5.l, v127.h ; encoding: [0xff,0xc1,0x0a,0x7e]
3358+
3359+
v_sin_f16 v127.l, 0.5
3360+
// GFX11: v_sin_f16_e32 v127.l, 0.5 ; encoding: [0xf0,0xc0,0xfe,0x7e]
3361+
3362+
v_sin_f16 v5.h, src_scc
3363+
// GFX11: v_sin_f16_e32 v5.h, src_scc ; encoding: [0xfd,0xc0,0x0a,0x7f]
3364+
3365+
v_sin_f16 v127.h, 0xfe0b
3366+
// GFX11: v_sin_f16_e32 v127.h, 0xfe0b ; encoding: [0xff,0xc0,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
33523367

33533368
v_sin_f32 v5, v1
33543369
// GFX11: v_sin_f32_e32 v5, v1 ; encoding: [0x01,0x6b,0x0a,0x7e]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s

Lines changed: 37 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2582,47 +2582,56 @@ v_sat_pk_u8_i16 v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:
25822582
v_sat_pk_u8_i16 v127.h, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
25832583
// GFX11: v_sat_pk_u8_i16_dpp v127.h, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7f,0xff,0x6f,0x05,0x30]
25842584

2585-
v_sin_f16 v5, v1 quad_perm:[3,2,1,0]
2586-
// GFX11: v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
2585+
v_sin_f16 v5.l, v1.l quad_perm:[3,2,1,0]
2586+
// GFX11: v_sin_f16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
25872587

2588-
v_sin_f16 v5, v1 quad_perm:[0,1,2,3]
2589-
// GFX11: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
2588+
v_sin_f16 v5.l, v1.l quad_perm:[0,1,2,3]
2589+
// GFX11: v_sin_f16_dpp v5.l, v1.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
25902590

2591-
v_sin_f16 v5, v1 row_mirror
2592-
// GFX11: v_sin_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0xff]
2591+
v_sin_f16 v5.l, v1.l row_mirror
2592+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0xff]
25932593

2594-
v_sin_f16 v5, v1 row_half_mirror
2595-
// GFX11: v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0xff]
2594+
v_sin_f16 v5.l, v1.l row_half_mirror
2595+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0xff]
25962596

2597-
v_sin_f16 v5, v1 row_shl:1
2598-
// GFX11: v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0xff]
2597+
v_sin_f16 v5.l, v1.l row_shl:1
2598+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0xff]
25992599

2600-
v_sin_f16 v5, v1 row_shl:15
2601-
// GFX11: v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
2600+
v_sin_f16 v5.l, v1.l row_shl:15
2601+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
26022602

2603-
v_sin_f16 v5, v1 row_shr:1
2604-
// GFX11: v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0xff]
2603+
v_sin_f16 v5.l, v1.l row_shr:1
2604+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0xff]
26052605

2606-
v_sin_f16 v5, v1 row_shr:15
2607-
// GFX11: v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
2606+
v_sin_f16 v5.l, v1.l row_shr:15
2607+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
26082608

2609-
v_sin_f16 v5, v1 row_ror:1
2610-
// GFX11: v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0xff]
2609+
v_sin_f16 v5.l, v1.l row_ror:1
2610+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0xff]
26112611

2612-
v_sin_f16 v5, v1 row_ror:15
2613-
// GFX11: v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
2612+
v_sin_f16 v5.l, v1.l row_ror:15
2613+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
26142614

2615-
v_sin_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
2616-
// GFX11: v_sin_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x50,0x01,0xff]
2615+
v_sin_f16 v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf
2616+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x50,0x01,0xff]
26172617

2618-
v_sin_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
2619-
// GFX11: v_sin_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
2618+
v_sin_f16 v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1
2619+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
26202620

2621-
v_sin_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2622-
// GFX11: v_sin_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x60,0x09,0x13]
2621+
v_sin_f16 v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
2622+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x60,0x09,0x13]
26232623

2624-
v_sin_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2625-
// GFX11: v_sin_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
2624+
v_sin_f16 v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
2625+
// GFX11: v_sin_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
2626+
2627+
v_sin_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
2628+
// GFX11: v_sin_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
2629+
2630+
v_sin_f16 v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2631+
// GFX11: v_sin_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x09,0x13]
2632+
2633+
v_sin_f16 v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2634+
// GFX11: v_sin_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x35,0x30]
26262635

26272636
v_sin_f32 v5, v1 quad_perm:[3,2,1,0]
26282637
// GFX11: v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0xff]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -614,14 +614,23 @@ v_sat_pk_u8_i16 v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
614614
v_sat_pk_u8_i16 v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
615615
// GFX11: v_sat_pk_u8_i16_dpp v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc4,0xfe,0x7f,0xff,0x00,0x00,0x00]
616616

617-
v_sin_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
618-
// GFX11: v_sin_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
617+
v_sin_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
618+
// GFX11: v_sin_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
619619

620-
v_sin_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
621-
// GFX11: v_sin_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
620+
v_sin_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1
621+
// GFX11: v_sin_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
622622

623-
v_sin_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
624-
// GFX11: v_sin_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
623+
v_sin_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
624+
// GFX11: v_sin_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
625+
626+
v_sin_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
627+
// GFX11: v_sin_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x77,0x39,0x05]
628+
629+
v_sin_f16 v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1
630+
// GFX11: v_sin_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05]
631+
632+
v_sin_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
633+
// GFX11: v_sin_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00]
625634

626635
v_sin_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
627636
// GFX11: v_sin_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -779,6 +779,12 @@ v_sat_pk_u8_i16_e32 v199.l, v5.l quad_perm:[3,2,1,0]
779779
v_sin_f16_e32 v128, 0xfe0b
780780
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
781781

782+
v_sin_f16_e32 v128.h, 0xfe0b
783+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
784+
785+
v_sin_f16_e32 v128.l, 0xfe0b
786+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
787+
782788
v_sin_f16_e32 v255, v1
783789
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
784790

@@ -788,6 +794,24 @@ v_sin_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
788794
v_sin_f16_e32 v255, v1 quad_perm:[3,2,1,0]
789795
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
790796

797+
v_sin_f16_e32 v255.h, v1.h
798+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
799+
800+
v_sin_f16_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
801+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
802+
803+
v_sin_f16_e32 v255.h, v1.h quad_perm:[3,2,1,0]
804+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
805+
806+
v_sin_f16_e32 v255.l, v1.l
807+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
808+
809+
v_sin_f16_e32 v255.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
810+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
811+
812+
v_sin_f16_e32 v255.l, v1.l quad_perm:[3,2,1,0]
813+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
814+
791815
v_sin_f16_e32 v5, v199
792816
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
793817

@@ -797,6 +821,24 @@ v_sin_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
797821
v_sin_f16_e32 v5, v199 quad_perm:[3,2,1,0]
798822
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
799823

824+
v_sin_f16_e32 v5.h, v199.h
825+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
826+
827+
v_sin_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
828+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
829+
830+
v_sin_f16_e32 v5.h, v199.h quad_perm:[3,2,1,0]
831+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
832+
833+
v_sin_f16_e32 v5.l, v199.l
834+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
835+
836+
v_sin_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
837+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
838+
839+
v_sin_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
840+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
841+
800842
v_sqrt_f16_e32 v128.h, 0xfe0b
801843
// GFX11: :[[@LINE-1]]:16: error: invalid operand for instruction
802844

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