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1 parent 2da57f8 commit 34ecc4bCopy full SHA for 34ecc4b
llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -79,6 +79,12 @@ tablegen("RISCVGenRegisterBank") {
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td_file = "RISCV.td"
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}
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+tablegen("RISCVGenSDNodeInfo") {
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+ visibility = [ ":LLVMRISCVCodeGen" ]
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+ args = [ "-gen-sd-node-info" ]
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+ td_file = "RISCV.td"
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+}
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+
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static_library("LLVMRISCVCodeGen") {
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deps = [
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":RISCVGenCompressInstEmitter",
@@ -90,6 +96,7 @@ static_library("LLVMRISCVCodeGen") {
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":RISCVGenPostLegalizeGICombiner",
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":RISCVGenPreLegalizeGICombiner",
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":RISCVGenRegisterBank",
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+ ":RISCVGenSDNodeInfo",
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# See https://reviews.llvm.org/D69130
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"AsmParser:RISCVGenAsmMatcher",
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