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Changes from pull/111452 + use the new recede
Change-Id: I9d6ba224894947f6e94df9ece3faf3f73d4e700f
1 parent b6e86d8 commit 35ab173

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2 files changed

+2
-11
lines changed

2 files changed

+2
-11
lines changed

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -352,16 +352,6 @@ static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
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return LastUseMask;
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}
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/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
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static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI,
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bool TrackLaneMasks, Register RegUnit,
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SlotIndex Pos) {
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return getLanesWithProperty(
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LIS, MRI, TrackLaneMasks, RegUnit, Pos, LaneBitmask::getAll(),
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[](const LiveRange &LR, SlotIndex Pos) { return LR.liveAt(Pos); });
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}
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///////////////////////////////////////////////////////////////////////////////
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// GCNRPTracker
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llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,8 @@ static void getRegisterPressures(
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NewPressure = TempDownwardTracker.bumpDownwardPressure(MI, SRI);
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} else {
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GCNUpwardRPTracker TempUpwardTracker(UpwardTracker);
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NewPressure = TempUpwardTracker.bumpUpwardPressure(MI, SRI);
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TempUpwardTracker.recede(*MI);
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NewPressure = TempUpwardTracker.getPressure();
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}
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Pressure[AMDGPU::RegisterPressureSets::SReg_32] = NewPressure.getSGPRNum();
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Pressure[AMDGPU::RegisterPressureSets::VGPR_32] =

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