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Reapply: Convert many LivePhysRegs uses to LiveRegUnits
This only converts the instances where all that is needed is to change the variable type name. Basically, anything that involves a function that LiveRegUnits does not directly have was skipped to play it safe.
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5 files changed

+28
-30
lines changed

5 files changed

+28
-30
lines changed

‎llvm/lib/CodeGen/ReachingDefAnalysis.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,10 @@
66
//
77
//===----------------------------------------------------------------------===//
88

9-
#include "llvm/ADT/SmallSet.h"
10-
#include "llvm/ADT/SetOperations.h"
11-
#include "llvm/CodeGen/LivePhysRegs.h"
129
#include "llvm/CodeGen/ReachingDefAnalysis.h"
10+
#include "llvm/ADT/SetOperations.h"
11+
#include "llvm/ADT/SmallSet.h"
12+
#include "llvm/CodeGen/LiveRegUnits.h"
1313
#include "llvm/CodeGen/TargetRegisterInfo.h"
1414
#include "llvm/CodeGen/TargetSubtargetInfo.h"
1515
#include "llvm/Support/Debug.h"
@@ -421,9 +421,9 @@ void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB,
421421
return;
422422

423423
VisitedBBs.insert(MBB);
424-
LivePhysRegs LiveRegs(*TRI);
424+
LiveRegUnits LiveRegs(*TRI);
425425
LiveRegs.addLiveOuts(*MBB);
426-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
426+
if (LiveRegs.available(PhysReg))
427427
return;
428428

429429
if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg))
@@ -469,19 +469,19 @@ MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
469469
bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI,
470470
MCRegister PhysReg) const {
471471
MachineBasicBlock *MBB = MI->getParent();
472-
LivePhysRegs LiveRegs(*TRI);
472+
LiveRegUnits LiveRegs(*TRI);
473473
LiveRegs.addLiveOuts(*MBB);
474474

475475
// Yes if the register is live out of the basic block.
476-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
476+
if (!LiveRegs.available(PhysReg))
477477
return true;
478478

479479
// Walk backwards through the block to see if the register is live at some
480480
// point.
481481
for (MachineInstr &Last :
482482
instructionsWithoutDebug(MBB->instr_rbegin(), MBB->instr_rend())) {
483483
LiveRegs.stepBackward(Last);
484-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
484+
if (!LiveRegs.available(PhysReg))
485485
return InstIds.lookup(&Last) > InstIds.lookup(MI);
486486
}
487487
return false;
@@ -504,9 +504,9 @@ bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI,
504504
bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
505505
MCRegister PhysReg) const {
506506
MachineBasicBlock *MBB = MI->getParent();
507-
LivePhysRegs LiveRegs(*TRI);
507+
LiveRegUnits LiveRegs(*TRI);
508508
LiveRegs.addLiveOuts(*MBB);
509-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
509+
if (LiveRegs.available(PhysReg))
510510
return false;
511511

512512
auto Last = MBB->getLastNonDebugInstr();
@@ -525,9 +525,9 @@ bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
525525
MachineInstr *
526526
ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
527527
MCRegister PhysReg) const {
528-
LivePhysRegs LiveRegs(*TRI);
528+
LiveRegUnits LiveRegs(*TRI);
529529
LiveRegs.addLiveOuts(*MBB);
530-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
530+
if (LiveRegs.available(PhysReg))
531531
return nullptr;
532532

533533
auto Last = MBB->getLastNonDebugInstr();

‎llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
1212
#include "SIRegisterInfo.h"
1313
#include "llvm/ADT/SmallVector.h"
14-
#include "llvm/CodeGen/LivePhysRegs.h"
14+
#include "llvm/CodeGen/LiveRegUnits.h"
1515
#include "llvm/CodeGen/MachineFunctionPass.h"
1616
#include "llvm/CodeGen/MachineOperand.h"
1717
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -313,7 +313,7 @@ MachineBasicBlock::reverse_iterator SIOptimizeExecMasking::findExecCopy(
313313
return E;
314314
}
315315

316-
// XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
316+
// XXX - Seems LiveRegUnits doesn't work correctly since it will incorrectly
317317
// report the register as unavailable because a super-register with a lane mask
318318
// is unavailable.
319319
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
@@ -383,7 +383,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
383383
MCRegister Reg,
384384
bool UseLiveOuts,
385385
bool IgnoreStart) const {
386-
LivePhysRegs LR(*TRI);
386+
LiveRegUnits LR(*TRI);
387387
if (UseLiveOuts)
388388
LR.addLiveOuts(*Stop.getParent());
389389

@@ -396,7 +396,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
396396
LR.stepBackward(*A);
397397
}
398398

399-
return !LR.available(*MRI, Reg);
399+
return !LR.available(Reg);
400400
}
401401

402402
// Determine if a register Reg is not re-defined and still in use

‎llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
#include "llvm/ADT/Statistic.h"
3232
#include "llvm/ADT/iterator_range.h"
3333
#include "llvm/Analysis/AliasAnalysis.h"
34-
#include "llvm/CodeGen/LivePhysRegs.h"
34+
#include "llvm/CodeGen/LiveRegUnits.h"
3535
#include "llvm/CodeGen/MachineBasicBlock.h"
3636
#include "llvm/CodeGen/MachineDominators.h"
3737
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -109,7 +109,7 @@ namespace {
109109
const ARMSubtarget *STI;
110110
const TargetLowering *TL;
111111
ARMFunctionInfo *AFI;
112-
LivePhysRegs LiveRegs;
112+
LiveRegUnits LiveRegs;
113113
RegisterClassInfo RegClassInfo;
114114
MachineBasicBlock::const_iterator LiveRegPos;
115115
bool LiveRegsValid;
@@ -589,7 +589,7 @@ unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
589589
}
590590

591591
for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
592-
if (LiveRegs.available(MF->getRegInfo(), Reg))
592+
if (LiveRegs.available(Reg))
593593
return Reg;
594594
return 0;
595595
}

‎llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -612,11 +612,11 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
612612

613613
static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
614614
const BitVector &PopFriendly,
615-
const LivePhysRegs &UsedRegs, unsigned &PopReg,
615+
const LiveRegUnits &UsedRegs, unsigned &PopReg,
616616
unsigned &TmpReg, MachineRegisterInfo &MRI) {
617617
PopReg = TmpReg = 0;
618618
for (auto Reg : GPRsNoLRSP.set_bits()) {
619-
if (UsedRegs.available(MRI, Reg)) {
619+
if (UsedRegs.available(Reg)) {
620620
// Remember the first pop-friendly register and exit.
621621
if (PopFriendly.test(Reg)) {
622622
PopReg = Reg;
@@ -684,7 +684,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
684684
// Look for a temporary register to use.
685685
// First, compute the liveness information.
686686
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
687-
LivePhysRegs UsedRegs(TRI);
687+
LiveRegUnits UsedRegs(TRI);
688688
UsedRegs.addLiveOuts(MBB);
689689
// The semantic of pristines changed recently and now,
690690
// the callee-saved registers that are touched in the function

‎llvm/test/CodeGen/Thumb/PR35481.ll

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
1818
; CHECK-V4T-NEXT: movs r2, #3
1919
; CHECK-V4T-NEXT: movs r3, #4
2020
; CHECK-V4T-NEXT: bl g
21+
; CHECK-V4T-NEXT: ldr r7, [sp, #4]
22+
; CHECK-V4T-NEXT: mov lr, r7
2123
; CHECK-V4T-NEXT: pop {r7}
22-
; CHECK-V4T-NEXT: mov r12, r0
23-
; CHECK-V4T-NEXT: pop {r0}
24-
; CHECK-V4T-NEXT: mov lr, r0
25-
; CHECK-V4T-NEXT: mov r0, r12
24+
; CHECK-V4T-NEXT: add sp, #4
2625
; CHECK-V4T-NEXT: bx lr
2726
;
2827
; CHECK-V8M-LABEL: f:
@@ -36,11 +35,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
3635
; CHECK-V8M-NEXT: movs r1, #2
3736
; CHECK-V8M-NEXT: movs r2, #3
3837
; CHECK-V8M-NEXT: movs r3, #4
38+
; CHECK-V8M-NEXT: ldr r7, [sp, #4]
39+
; CHECK-V8M-NEXT: mov lr, r7
3940
; CHECK-V8M-NEXT: pop {r7}
40-
; CHECK-V8M-NEXT: mov r12, r0
41-
; CHECK-V8M-NEXT: pop {r0}
42-
; CHECK-V8M-NEXT: mov lr, r0
43-
; CHECK-V8M-NEXT: mov r0, r12
41+
; CHECK-V8M-NEXT: add sp, #4
4442
; CHECK-V8M-NEXT: b g
4543
entry:
4644
%call = tail call i32 @h(i32 1)

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