@@ -18777,22 +18777,15 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
18777
18777
Function *F = CGM.getIntrinsic(Intrin, { Src0->getType() });
18778
18778
return Builder.CreateCall(F, { Src0, Builder.getFalse() });
18779
18779
}
18780
- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
18781
18780
case AMDGPU::BI__builtin_amdgcn_global_atomic_fmin_f64:
18782
18781
case AMDGPU::BI__builtin_amdgcn_global_atomic_fmax_f64:
18783
18782
case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f64:
18784
18783
case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmin_f64:
18785
18784
case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmax_f64:
18786
- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f32:
18787
- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16: {
18785
+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f32: {
18788
18786
Intrinsic::ID IID;
18789
18787
llvm::Type *ArgTy = llvm::Type::getDoubleTy(getLLVMContext());
18790
18788
switch (BuiltinID) {
18791
- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
18792
- ArgTy = llvm::FixedVectorType::get(
18793
- llvm::Type::getHalfTy(getLLVMContext()), 2);
18794
- IID = Intrinsic::amdgcn_global_atomic_fadd;
18795
- break;
18796
18789
case AMDGPU::BI__builtin_amdgcn_global_atomic_fmin_f64:
18797
18790
IID = Intrinsic::amdgcn_global_atomic_fmin;
18798
18791
break;
@@ -18812,11 +18805,6 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
18812
18805
ArgTy = llvm::Type::getFloatTy(getLLVMContext());
18813
18806
IID = Intrinsic::amdgcn_flat_atomic_fadd;
18814
18807
break;
18815
- case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16:
18816
- ArgTy = llvm::FixedVectorType::get(
18817
- llvm::Type::getHalfTy(getLLVMContext()), 2);
18818
- IID = Intrinsic::amdgcn_flat_atomic_fadd;
18819
- break;
18820
18808
}
18821
18809
llvm::Value *Addr = EmitScalarExpr(E->getArg(0));
18822
18810
llvm::Value *Val = EmitScalarExpr(E->getArg(1));
@@ -19217,7 +19205,9 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
19217
19205
case AMDGPU::BI__builtin_amdgcn_ds_fminf:
19218
19206
case AMDGPU::BI__builtin_amdgcn_ds_fmaxf:
19219
19207
case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f32:
19220
- case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64: {
19208
+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64:
19209
+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
19210
+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16: {
19221
19211
llvm::AtomicRMWInst::BinOp BinOp;
19222
19212
switch (BuiltinID) {
19223
19213
case AMDGPU::BI__builtin_amdgcn_atomic_inc32:
@@ -19235,6 +19225,8 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
19235
19225
case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_v2bf16:
19236
19226
case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f32:
19237
19227
case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64:
19228
+ case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16:
19229
+ case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16:
19238
19230
BinOp = llvm::AtomicRMWInst::FAdd;
19239
19231
break;
19240
19232
case AMDGPU::BI__builtin_amdgcn_ds_fminf:
0 commit comments