[RISCV] Merge rv32 and rv64 Zvb* intrinsic tests. NFC

There was some duplication between these tests and
we can merge them by checking __riscv_xlen for the parts
that aren't duplicated.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D156851

Author: topperc

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c

@@ -1,8 +1,16 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBB
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbb -emit-llvm %s -o - \
 // RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBB
 
+// RV32ZBB-LABEL: @orc_b_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
+//
 // RV64ZBB-LABEL: @orc_b_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
@@ -12,6 +20,7 @@ unsigned int orc_b_32(unsigned int a) {
   return __builtin_riscv_orc_b_32(a);
 }
 
+#if __riscv_xlen == 64
 // RV64ZBB-LABEL: @orc_b_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[A:%.*]])
@@ -20,7 +29,13 @@ unsigned int orc_b_32(unsigned int a) {
 unsigned long orc_b_64(unsigned long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+#endif
 
+// RV32ZBB-LABEL: @clz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
+//
 // RV64ZBB-LABEL: @clz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
@@ -30,6 +45,7 @@ unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
+#if __riscv_xlen == 64
 // RV64ZBB-LABEL: @clz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
@@ -39,7 +55,13 @@ unsigned int clz_32(unsigned int a) {
 unsigned int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
+#endif
 
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
+//
 // RV64ZBB-LABEL: @ctz_32(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
@@ -49,6 +71,7 @@ unsigned int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
+#if __riscv_xlen == 64
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false)
@@ -58,3 +81,4 @@ unsigned int ctz_32(unsigned int a) {
 unsigned int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
+#endif

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c

@@ -1,9 +1,12 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBC
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbc -emit-llvm %s -o - \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBC
 
 #include <stdint.h>
 
+#if __riscv_xlen == 64
 // RV64ZBC-LABEL: @clmul_64(
 // RV64ZBC-NEXT:  entry:
 // RV64ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
@@ -48,7 +51,19 @@ uint64_t clmulh_64(uint64_t a, uint64_t b) {
 uint64_t clmulr_64(uint64_t a, uint64_t b) {
   return __builtin_riscv_clmulr_64(a, b);
 }
+#endif
 
+// RV32ZBC-LABEL: @clmul_32(
+// RV32ZBC-NEXT:  entry:
+// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT:    ret i32 [[TMP2]]
+//
 // RV64ZBC-LABEL: @clmul_32(
 // RV64ZBC-NEXT:  entry:
 // RV64ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
@@ -64,3 +79,34 @@ uint32_t clmul_32(uint32_t a, uint32_t b) {
   return __builtin_riscv_clmul_32(a, b);
 }
 
+#if __riscv_xlen == 32
+// RV32ZBC-LABEL: @clmulh_32(
+// RV32ZBC-NEXT:  entry:
+// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t clmulh_32(uint32_t a, uint32_t b) {
+  return __builtin_riscv_clmulh_32(a, b);
+}
+
+// RV32ZBC-LABEL: @clmulr_32(
+// RV32ZBC-NEXT:  entry:
+// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT:    ret i32 [[TMP2]]
+//
+uint32_t clmulr_32(uint32_t a, uint32_t b) {
+  return __builtin_riscv_clmulr_32(a, b);
+}
+#endif

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c

@@ -2,19 +2,40 @@
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkb -emit-llvm %s -o - \
 // RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBKB
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBKB
 
 #include <stdint.h>
 
-// RV32ZBKB-LABEL: @brev8(
+// RV32ZBKB-LABEL: @brev8_32(
 // RV32ZBKB-NEXT:  entry:
 // RV32ZBKB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
 // RV32ZBKB-NEXT:    ret i32 [[TMP0]]
 //
-uint32_t brev8(uint32_t rs1)
+// RV64ZBKB-LABEL: @brev8_32(
+// RV64ZBKB-NEXT:  entry:
+// RV64ZBKB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
+// RV64ZBKB-NEXT:    ret i32 [[TMP0]]
+//
+uint32_t brev8_32(uint32_t rs1)
 {
   return __builtin_riscv_brev8_32(rs1);
 }
 
+#if __riscv_xlen == 64
+// RV64ZBKB-LABEL: @brev8_64(
+// RV64ZBKB-NEXT:  entry:
+// RV64ZBKB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[RS1:%.*]])
+// RV64ZBKB-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t brev8_64(uint64_t rs1)
+{
+  return __builtin_riscv_brev8_64(rs1);
+}
+#endif
+
+#if __riscv_xlen == 32
 // RV32ZBKB-LABEL: @zip(
 // RV32ZBKB-NEXT:  entry:
 // RV32ZBKB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[RS1:%.*]])
@@ -34,3 +55,4 @@ uint32_t unzip(uint32_t rs1)
 {
   return __builtin_riscv_unzip_32(rs1);
 }
+#endif