clang format

Author: MDevereau

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -326,7 +326,8 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
     return false;
   }
 
-  template <unsigned BaseReg, unsigned Max> bool ImmToTile(SDValue N, SDValue &Imm) {
+  template <unsigned BaseReg, unsigned Max>
+  bool ImmToTile(SDValue N, SDValue &Imm) {
     if (auto *CI = dyn_cast<ConstantSDNode>(N)) {
       uint64_t C = CI->getZExtValue();
 

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -2754,12 +2754,11 @@ MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
   if (IsSpill) {
     MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::STR_TX));
     MIB.addReg(MI.getOperand(0).getReg());
-  }
-  else
+  } else
     MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(AArch64::LDR_TX),
                   MI.getOperand(0).getReg());
   MIB.add(MI.getOperand(1)); // Base
-  MI.eraseFromParent(); // The pseudo is gone now.
+  MI.eraseFromParent();      // The pseudo is gone now.
   return BB;
 }
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -442,7 +442,7 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
 
   if (MF.getSubtarget<AArch64Subtarget>().hasSME2()) {
     for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true);
-      SubReg.isValid(); ++SubReg)
+         SubReg.isValid(); ++SubReg)
       Reserved.set(*SubReg);
   }