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[RISCV][GISel] Add support for G_FPTOSI/G_FPTOUI with F and D extensions.
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8 files changed

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8 files changed

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‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
217217
(ST.hasStdExtD() && typeIs(0, s64)(Query));
218218
});
219219

220+
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
221+
.legalIf([=, &ST](const LegalityQuery &Query) -> bool {
222+
return typeInSet(0, {s32, sXLen})(Query) &&
223+
((ST.hasStdExtF() && typeIs(1, s32)(Query)) ||
224+
(ST.hasStdExtD() && typeIs(1, s64)(Query)));
225+
})
226+
.widenScalarToNextPow2(0)
227+
.clampScalar(0, s32, sXLen);
228+
220229
getLegacyLegalizerInfo().computeTables();
221230
}
222231

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -205,14 +205,20 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
205205
case TargetOpcode::G_FPEXT:
206206
case TargetOpcode::G_FPTRUNC: {
207207
LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
208-
(void)ToTy;
209208
LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
210-
(void)FromTy;
211209
OperandsMapping =
212210
getOperandsMapping({getFPValueMapping(ToTy.getSizeInBits()),
213211
getFPValueMapping(FromTy.getSizeInBits())});
214212
break;
215213
}
214+
case TargetOpcode::G_FPTOSI:
215+
case TargetOpcode::G_FPTOUI: {
216+
LLT Ty = MRI.getType(MI.getOperand(1).getReg());
217+
OperandsMapping =
218+
getOperandsMapping({GPRValueMapping,
219+
getFPValueMapping(Ty.getSizeInBits())});
220+
break;
221+
}
216222
case TargetOpcode::G_FCONSTANT: {
217223
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
218224
OperandsMapping =

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv32.mir

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,92 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
5+
---
6+
name: fptosi_s32_s32
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.1:
12+
liveins: $f10_f
13+
14+
; CHECK-LABEL: name: fptosi_s32_s32
15+
; CHECK: liveins: $f10_f
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
18+
; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[COPY]], 1
19+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]]
20+
; CHECK-NEXT: PseudoRET implicit $x10
21+
%0:fprb(s32) = COPY $f10_f
22+
%1:gprb(s32) = G_FPTOSI %0(s32)
23+
$x10 = COPY %1(s32)
24+
PseudoRET implicit $x10
25+
26+
...
27+
---
28+
name: fptoui_s32_s32
29+
legalized: true
30+
regBankSelected: true
31+
tracksRegLiveness: true
32+
body: |
33+
bb.1:
34+
liveins: $f10_f
35+
36+
; CHECK-LABEL: name: fptoui_s32_s32
37+
; CHECK: liveins: $f10_f
38+
; CHECK-NEXT: {{ $}}
39+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
40+
; CHECK-NEXT: [[FCVT_WU_S:%[0-9]+]]:gpr = nofpexcept FCVT_WU_S [[COPY]], 1
41+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]]
42+
; CHECK-NEXT: PseudoRET implicit $x10
43+
%0:fprb(s32) = COPY $f10_f
44+
%1:gprb(s32) = G_FPTOUI %0(s32)
45+
$x10 = COPY %1(s32)
46+
PseudoRET implicit $x10
47+
48+
...
49+
---
50+
name: fptosi_s32_s64
51+
legalized: true
52+
regBankSelected: true
53+
tracksRegLiveness: true
54+
body: |
55+
bb.1:
56+
liveins: $f10_d
57+
58+
; CHECK-LABEL: name: fptosi_s32_s64
59+
; CHECK: liveins: $f10_d
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
62+
; CHECK-NEXT: [[FCVT_W_D:%[0-9]+]]:gpr = nofpexcept FCVT_W_D [[COPY]], 1
63+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]]
64+
; CHECK-NEXT: PseudoRET implicit $x10
65+
%0:fprb(s64) = COPY $f10_d
66+
%1:gprb(s32) = G_FPTOSI %0(s64)
67+
$x10 = COPY %1(s32)
68+
PseudoRET implicit $x10
69+
70+
...
71+
---
72+
name: fptoui_s32_s64
73+
legalized: true
74+
regBankSelected: true
75+
tracksRegLiveness: true
76+
body: |
77+
bb.1:
78+
liveins: $f10_d
79+
80+
; CHECK-LABEL: name: fptoui_s32_s64
81+
; CHECK: liveins: $f10_d
82+
; CHECK-NEXT: {{ $}}
83+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
84+
; CHECK-NEXT: [[FCVT_WU_D:%[0-9]+]]:gpr = nofpexcept FCVT_WU_D [[COPY]], 1
85+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]]
86+
; CHECK-NEXT: PseudoRET implicit $x10
87+
%0:fprb(s64) = COPY $f10_d
88+
%1:gprb(s32) = G_FPTOUI %0(s64)
89+
$x10 = COPY %1(s32)
90+
PseudoRET implicit $x10
91+
92+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir

Lines changed: 184 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,184 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
5+
---
6+
name: fptosi_s32_s32
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.1:
12+
liveins: $f10_f
13+
14+
; CHECK-LABEL: name: fptosi_s32_s32
15+
; CHECK: liveins: $f10_f
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
18+
; CHECK-NEXT: [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[COPY]], 1
19+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_S]]
20+
; CHECK-NEXT: PseudoRET implicit $x10
21+
%0:fprb(s32) = COPY $f10_f
22+
%1:gprb(s32) = G_FPTOSI %0(s32)
23+
%2:gprb(s64) = G_ANYEXT %1(s32)
24+
$x10 = COPY %2(s64)
25+
PseudoRET implicit $x10
26+
27+
...
28+
---
29+
name: fptoui_s32_s32
30+
legalized: true
31+
regBankSelected: true
32+
tracksRegLiveness: true
33+
body: |
34+
bb.1:
35+
liveins: $f10_f
36+
37+
; CHECK-LABEL: name: fptoui_s32_s32
38+
; CHECK: liveins: $f10_f
39+
; CHECK-NEXT: {{ $}}
40+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
41+
; CHECK-NEXT: [[FCVT_WU_S:%[0-9]+]]:gpr = nofpexcept FCVT_WU_S [[COPY]], 1
42+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_S]]
43+
; CHECK-NEXT: PseudoRET implicit $x10
44+
%0:fprb(s32) = COPY $f10_f
45+
%1:gprb(s32) = G_FPTOUI %0(s32)
46+
%2:gprb(s64) = G_ANYEXT %1(s32)
47+
$x10 = COPY %2(s64)
48+
PseudoRET implicit $x10
49+
50+
...
51+
---
52+
name: fptosi_s64_s32
53+
legalized: true
54+
regBankSelected: true
55+
tracksRegLiveness: true
56+
body: |
57+
bb.1:
58+
liveins: $f10_f
59+
60+
; CHECK-LABEL: name: fptosi_s64_s32
61+
; CHECK: liveins: $f10_f
62+
; CHECK-NEXT: {{ $}}
63+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
64+
; CHECK-NEXT: [[FCVT_L_S:%[0-9]+]]:gpr = nofpexcept FCVT_L_S [[COPY]], 1
65+
; CHECK-NEXT: $x10 = COPY [[FCVT_L_S]]
66+
; CHECK-NEXT: PseudoRET implicit $x10
67+
%0:fprb(s32) = COPY $f10_f
68+
%1:gprb(s64) = G_FPTOSI %0(s32)
69+
$x10 = COPY %1(s64)
70+
PseudoRET implicit $x10
71+
72+
...
73+
---
74+
name: fptoui_s64_s32
75+
legalized: true
76+
regBankSelected: true
77+
tracksRegLiveness: true
78+
body: |
79+
bb.1:
80+
liveins: $f10_f
81+
82+
; CHECK-LABEL: name: fptoui_s64_s32
83+
; CHECK: liveins: $f10_f
84+
; CHECK-NEXT: {{ $}}
85+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
86+
; CHECK-NEXT: [[FCVT_LU_S:%[0-9]+]]:gpr = nofpexcept FCVT_LU_S [[COPY]], 1
87+
; CHECK-NEXT: $x10 = COPY [[FCVT_LU_S]]
88+
; CHECK-NEXT: PseudoRET implicit $x10
89+
%0:fprb(s32) = COPY $f10_f
90+
%1:gprb(s64) = G_FPTOUI %0(s32)
91+
$x10 = COPY %1(s64)
92+
PseudoRET implicit $x10
93+
94+
...
95+
---
96+
name: fptosi_s32_s64
97+
legalized: true
98+
regBankSelected: true
99+
tracksRegLiveness: true
100+
body: |
101+
bb.1:
102+
liveins: $f10_d
103+
104+
; CHECK-LABEL: name: fptosi_s32_s64
105+
; CHECK: liveins: $f10_d
106+
; CHECK-NEXT: {{ $}}
107+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
108+
; CHECK-NEXT: [[FCVT_W_D:%[0-9]+]]:gpr = nofpexcept FCVT_W_D [[COPY]], 1
109+
; CHECK-NEXT: $x10 = COPY [[FCVT_W_D]]
110+
; CHECK-NEXT: PseudoRET implicit $x10
111+
%0:fprb(s64) = COPY $f10_d
112+
%1:gprb(s32) = G_FPTOSI %0(s64)
113+
%2:gprb(s64) = G_ANYEXT %1(s32)
114+
$x10 = COPY %2(s64)
115+
PseudoRET implicit $x10
116+
117+
...
118+
---
119+
name: fptoui_s32_s64
120+
legalized: true
121+
regBankSelected: true
122+
tracksRegLiveness: true
123+
body: |
124+
bb.1:
125+
liveins: $f10_d
126+
127+
; CHECK-LABEL: name: fptoui_s32_s64
128+
; CHECK: liveins: $f10_d
129+
; CHECK-NEXT: {{ $}}
130+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
131+
; CHECK-NEXT: [[FCVT_WU_D:%[0-9]+]]:gpr = nofpexcept FCVT_WU_D [[COPY]], 1
132+
; CHECK-NEXT: $x10 = COPY [[FCVT_WU_D]]
133+
; CHECK-NEXT: PseudoRET implicit $x10
134+
%0:fprb(s64) = COPY $f10_d
135+
%1:gprb(s32) = G_FPTOUI %0(s64)
136+
%2:gprb(s64) = G_ANYEXT %1(s32)
137+
$x10 = COPY %2(s64)
138+
PseudoRET implicit $x10
139+
140+
...
141+
---
142+
name: fptosi_s64_s64
143+
legalized: true
144+
regBankSelected: true
145+
tracksRegLiveness: true
146+
body: |
147+
bb.1:
148+
liveins: $f10_d
149+
150+
; CHECK-LABEL: name: fptosi_s64_s64
151+
; CHECK: liveins: $f10_d
152+
; CHECK-NEXT: {{ $}}
153+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
154+
; CHECK-NEXT: [[FCVT_L_D:%[0-9]+]]:gpr = nofpexcept FCVT_L_D [[COPY]], 1
155+
; CHECK-NEXT: $x10 = COPY [[FCVT_L_D]]
156+
; CHECK-NEXT: PseudoRET implicit $x10
157+
%0:fprb(s64) = COPY $f10_d
158+
%1:gprb(s64) = G_FPTOSI %0(s64)
159+
$x10 = COPY %1(s64)
160+
PseudoRET implicit $x10
161+
162+
...
163+
---
164+
name: fptoui_s64_s64
165+
legalized: true
166+
regBankSelected: true
167+
tracksRegLiveness: true
168+
body: |
169+
bb.1:
170+
liveins: $f10_d
171+
172+
; CHECK-LABEL: name: fptoui_s64_s64
173+
; CHECK: liveins: $f10_d
174+
; CHECK-NEXT: {{ $}}
175+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
176+
; CHECK-NEXT: [[FCVT_LU_D:%[0-9]+]]:gpr = nofpexcept FCVT_LU_D [[COPY]], 1
177+
; CHECK-NEXT: $x10 = COPY [[FCVT_LU_D]]
178+
; CHECK-NEXT: PseudoRET implicit $x10
179+
%0:fprb(s64) = COPY $f10_d
180+
%1:gprb(s64) = G_FPTOUI %0(s64)
181+
$x10 = COPY %1(s64)
182+
PseudoRET implicit $x10
183+
184+
...

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