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AMDGPU: Replace test uses of ptr addrspace(5) undef with poison (#131101)
1 parent ad99368 commit 37c8792

15 files changed

+29
-29
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ bb8:
183183
br i1 %tmp10, label %bb11, label %bb12
184184

185185
bb11:
186-
store float 4.0, ptr addrspace(5) undef, align 4
186+
store float 4.0, ptr addrspace(5) poison, align 4
187187
br label %bb12
188188

189189
bb12:

‎llvm/test/CodeGen/AMDGPU/collapse-endcf.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1360,7 +1360,7 @@ bb2: ; preds = %bb1
13601360
br i1 %tmp3, label %bb4, label %bb10
13611361

13621362
bb4: ; preds = %bb2
1363-
%tmp6 = load float, ptr addrspace(5) undef
1363+
%tmp6 = load float, ptr addrspace(5) poison
13641364
%tmp7 = fcmp olt float %tmp6, 0.0
13651365
br i1 %tmp7, label %bb8, label %Flow
13661366

@@ -1380,7 +1380,7 @@ Flow1: ; preds = %bb10
13801380
br label %bb1
13811381

13821382
bb12: ; preds = %bb10
1383-
store volatile <4 x float> %tmp11, ptr addrspace(5) undef, align 16
1383+
store volatile <4 x float> %tmp11, ptr addrspace(5) poison, align 16
13841384
ret void
13851385
}
13861386

‎llvm/test/CodeGen/AMDGPU/dag-divergence.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
; GCN: flat_load_dword
77
; GCN-NOT: s_load_dword s
88
define amdgpu_kernel void @private_load_maybe_divergent(ptr addrspace(4) %k, ptr %flat) {
9-
%load = load volatile i32, ptr addrspace(5) undef, align 4
9+
%load = load volatile i32, ptr addrspace(5) poison, align 4
1010
%gep = getelementptr inbounds i32, ptr addrspace(4) %k, i32 %load
1111
%maybe.not.uniform.load = load i32, ptr addrspace(4) %gep, align 4
1212
store i32 %maybe.not.uniform.load, ptr addrspace(1) poison

‎llvm/test/CodeGen/AMDGPU/debug-value.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ bb25: ; preds = %bb
3535

3636
bb28: ; preds = %bb25, %bb21
3737
%tmp29 = phi <4 x float> [ %tmp27, %bb25 ], [ %tmp24, %bb21 ]
38-
store <4 x float> %tmp29, ptr addrspace(5) undef, align 16
38+
store <4 x float> %tmp29, ptr addrspace(5) poison, align 16
3939
%tmp30 = getelementptr inbounds %struct.wombat, ptr addrspace(1) %arg, i64 %tmp2, i32 2, i64 2
4040
%tmp31 = load i32, ptr addrspace(1) %tmp30, align 4
4141
%tmp32 = sext i32 %tmp31 to i64

‎llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -255,7 +255,7 @@ define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 {
255255
bb:
256256
%tmp = alloca <4 x float>, align 16, addrspace(5)
257257
%tmp2 = insertelement <4 x float> poison, float %arg, i32 0
258-
store <4 x float> %tmp2, ptr addrspace(5) undef
258+
store <4 x float> %tmp2, ptr addrspace(5) poison
259259
%tmp3 = icmp eq i32 %arg1, 0
260260
br i1 %tmp3, label %bb4, label %bb5
261261

‎llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ name: scratch_load_lds_dword_ds_read
7777
body: |
7878
bb.0:
7979
$m0 = S_MOV_B32 0
80-
SCRATCH_LOAD_LDS_DWORD $vgpr0, 4, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(5) undef` + 4), (store (s32) into `ptr addrspace(3) undef` + 4)
80+
SCRATCH_LOAD_LDS_DWORD $vgpr0, 4, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(5) poison` + 4), (store (s32) into `ptr addrspace(3) undef` + 4)
8181
$vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `ptr addrspace(3) undef`)
8282
S_ENDPGM 0
8383

‎llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ if.end5.i362: ; preds = %if.then3.i356, %if.
104104
%conv612.i359 = sext i8 %5 to i32
105105
%sub13.i360 = add nsw i32 %conv612.i359, -48
106106
%cmp714.i361 = icmp ugt i32 %sub13.i360, 9
107-
store i8 0, ptr addrspace(5) undef, align 16
107+
store i8 0, ptr addrspace(5) poison, align 16
108108
%6 = load i8, ptr addrspace(1) getelementptr inbounds ([4096 x i8], ptr addrspace(1) @_RSENC_gDcd_______________________________, i64 0, i64 1153), align 1
109109
%arrayidx232250.1 = getelementptr inbounds [128 x i8], ptr addrspace(5) %pD10, i32 0, i32 1
110110
store i8 %6, ptr addrspace(5) %arrayidx232250.1, align 1

‎llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,13 +23,13 @@ body: |
2323
$sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
2424
$sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
2525
$vgpr0 = V_MOV_B32_e32 1, implicit $exec
26-
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) undef`)
26+
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) poison`)
2727
S_WAITCNT 127
2828
S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc
2929
S_WAITCNT 3855
3030
$vgpr0 = V_MOV_B32_e32 2, implicit $exec
3131
$vgpr1 = V_MOV_B32_e32 32772, implicit $exec
32-
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) undef`)
32+
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(5) poison`)
3333
S_CBRANCH_SCC0 %bb.1, implicit killed $scc
3434
3535
bb.2:
@@ -55,7 +55,7 @@ body: |
5555
S_WAITCNT 127
5656
$sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
5757
$vgpr0 = V_ADD_CO_U32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
58-
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, implicit $exec :: (load syncscope("agent-one-as") unordered (s32) from `ptr addrspace(1) undef`), (load syncscope("workgroup-one-as") seq_cst (s32) from `ptr addrspace(5) undef`)
58+
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, implicit $exec :: (load syncscope("agent-one-as") unordered (s32) from `ptr addrspace(1) undef`), (load syncscope("workgroup-one-as") seq_cst (s32) from `ptr addrspace(5) poison`)
5959
$vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
6060
$vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
6161
S_WAITCNT 3952

‎llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
1414
define amdgpu_kernel void @in_worklist_once() #0 {
1515
bb:
16-
%tmp = load i64, ptr addrspace(5) undef
16+
%tmp = load i64, ptr addrspace(5) poison
1717
br label %bb1
1818

1919
bb1: ; preds = %bb1, %bb

‎llvm/test/CodeGen/AMDGPU/operand-folding.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -130,7 +130,7 @@ define amdgpu_kernel void @no_fold_tied_subregister() #1 {
130130
; CHECK: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
131131
define void @no_extra_fold_on_same_opnd() #1 {
132132
entry:
133-
%s0 = load i32, ptr addrspace(5) undef, align 4
133+
%s0 = load i32, ptr addrspace(5) poison, align 4
134134
%s0.i64= zext i32 %s0 to i64
135135
br label %for.body.i.i
136136

‎llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
; OPTNONE-NOT: s_mov_b32
1919
; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
2020
define amdgpu_kernel void @store_to_undef() #0 {
21-
store volatile i32 0, ptr addrspace(5) undef
21+
store volatile i32 0, ptr addrspace(5) poison
2222
ret void
2323
}
2424

@@ -36,7 +36,7 @@ define amdgpu_kernel void @store_to_inttoptr() #0 {
3636
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]
3737
; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offen glc{{$}}
3838
define amdgpu_kernel void @load_from_undef() #0 {
39-
%ld = load volatile i32, ptr addrspace(5) undef
39+
%ld = load volatile i32, ptr addrspace(5) poison
4040
ret void
4141
}
4242

‎llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3
44

55
; CHECK-LABEL: @lds_promoted_alloca_select_invalid_pointer_operand(
66
; CHECK: %alloca = alloca i32
7-
; CHECK: select i1 undef, ptr addrspace(5) undef, ptr addrspace(5) %alloca
7+
; CHECK: select i1 undef, ptr addrspace(5) poison, ptr addrspace(5) %alloca
88
define amdgpu_kernel void @lds_promoted_alloca_select_invalid_pointer_operand() #0 {
99
%alloca = alloca i32, align 4, addrspace(5)
10-
%select = select i1 undef, ptr addrspace(5) undef, ptr addrspace(5) %alloca
10+
%select = select i1 undef, ptr addrspace(5) poison, ptr addrspace(5) %alloca
1111
store i32 0, ptr addrspace(5) %select, align 4
1212
ret void
1313
}
@@ -87,7 +87,7 @@ entry:
8787

8888
bb1:
8989
%ptr2 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %c
90-
%select0 = select i1 undef, ptr addrspace(5) undef, ptr addrspace(5) %ptr2
90+
%select0 = select i1 undef, ptr addrspace(5) poison, ptr addrspace(5) %ptr2
9191
store i32 0, ptr addrspace(5) %ptr1
9292
br label %bb2
9393

‎llvm/test/CodeGen/AMDGPU/sad.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(ptr addrspace(1) %out, i
105105
%t1 = select i1 %icmp1, i32 %a, i32 %b
106106

107107
%ret0 = sub i32 %t0, %t1
108-
store volatile i32 %ret0, ptr addrspace(5) undef
108+
store volatile i32 %ret0, ptr addrspace(5) poison
109109
%ret = add i32 %ret0, %c
110110

111111
store i32 %ret, ptr addrspace(1) %out
@@ -139,7 +139,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(ptr addrspace(1) %out, i
139139

140140
%ret0 = sub i32 %t0, %t1
141141
%ret = add i32 %ret0, %c
142-
store volatile i32 %ret, ptr addrspace(5) undef
142+
store volatile i32 %ret, ptr addrspace(5) poison
143143
store i32 %ret, ptr addrspace(1) %out
144144
ret void
145145
}
@@ -167,7 +167,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(ptr addrspace(1) %out, i
167167
; GCN-NEXT: s_endpgm
168168
%icmp0 = icmp ugt i32 %a, %b
169169
%t0 = select i1 %icmp0, i32 %a, i32 %b
170-
store volatile i32 %t0, ptr addrspace(5) undef
170+
store volatile i32 %t0, ptr addrspace(5) poison
171171

172172
%icmp1 = icmp ule i32 %a, %b
173173
%t1 = select i1 %icmp1, i32 %a, i32 %b
@@ -206,7 +206,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(ptr addrspace(1) %out, i
206206
%icmp1 = icmp ule i32 %a, %b
207207
%t1 = select i1 %icmp1, i32 %a, i32 %b
208208

209-
store volatile i32 %t1, ptr addrspace(5) undef
209+
store volatile i32 %t1, ptr addrspace(5) poison
210210

211211
%ret0 = sub i32 %t0, %t1
212212
%ret = add i32 %ret0, %c
@@ -238,7 +238,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(ptr addrspace(1) %out, i
238238
; GCN-NEXT: s_endpgm
239239
%icmp0 = icmp ugt i32 %a, %b
240240
%sub0 = sub i32 %a, %b
241-
store volatile i32 %sub0, ptr addrspace(5) undef
241+
store volatile i32 %sub0, ptr addrspace(5) poison
242242
%sub1 = sub i32 %b, %a
243243
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
244244

@@ -274,7 +274,7 @@ define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(ptr addrspace(1) %out
274274
%sub0 = sub i32 %a, %b
275275
%sub1 = sub i32 %b, %a
276276
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
277-
store volatile i32 %ret0, ptr addrspace(5) undef
277+
store volatile i32 %ret0, ptr addrspace(5) poison
278278

279279
%ret = add i32 %ret0, %c
280280

‎llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,18 +5,18 @@
55
; GCN: v_mov_b32_e32 [[V:v[0-9]+]], 42
66
; GCN: buffer_store_short [[V]],
77
define void @scalar_to_vector_i16() {
8-
%tmp = load <2 x i16>, ptr addrspace(5) undef
8+
%tmp = load <2 x i16>, ptr addrspace(5) poison
99
%tmp1 = insertelement <2 x i16> %tmp, i16 42, i64 0
10-
store <2 x i16> %tmp1, ptr addrspace(5) undef
10+
store <2 x i16> %tmp1, ptr addrspace(5) poison
1111
ret void
1212
}
1313

1414
; GCN-LABEL: {{^}}scalar_to_vector_f16:
1515
; GCN: v_mov_b32_e32 [[V:v[0-9]+]], 0x3c00
1616
; GCN: buffer_store_short [[V]],
1717
define void @scalar_to_vector_f16() {
18-
%tmp = load <2 x half>, ptr addrspace(5) undef
18+
%tmp = load <2 x half>, ptr addrspace(5) poison
1919
%tmp1 = insertelement <2 x half> %tmp, half 1.0, i64 0
20-
store <2 x half> %tmp1, ptr addrspace(5) undef
20+
store <2 x half> %tmp1, ptr addrspace(5) poison
2121
ret void
2222
}

‎llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ if.then4.i: ; preds = %entry
148148
%add1.i.i = add i32 %add.i.i, 0
149149
%mul.i.i.i.i = mul i32 %add1.i.i, 1103515245
150150
%add.i.i.i.i = add i32 %mul.i.i.i.i, 12345
151-
store i32 %add.i.i.i.i, ptr addrspace(5) undef, align 16
151+
store i32 %add.i.i.i.i, ptr addrspace(5) poison, align 16
152152
br label %shader_eval_surface.exit
153153

154154
shader_eval_surface.exit: ; preds = %entry

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