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[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218747
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‎llvm/lib/Target/ARM/ARM.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -392,6 +392,12 @@ def : ProcNoItin<"cortex-m4", [HasV7Ops,
392392
FeatureT2XtPk, FeatureVFP4,
393393
FeatureVFPOnlySP, FeatureD16,
394394
FeatureMClass]>;
395+
def : ProcNoItin<"cortex-m7", [HasV7Ops,
396+
FeatureThumb2, FeatureNoARM, FeatureDB,
397+
FeatureHWDiv, FeatureDSPThumb2,
398+
FeatureT2XtPk, FeatureFPARMv8,
399+
FeatureD16, FeatureMClass]>;
400+
395401

396402
// Swift uArch Processors.
397403
def : ProcessorModel<"swift", SwiftModel,

‎llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -667,7 +667,9 @@ void ARMAsmPrinter::emitAttributes() {
667667
ARMBuildAttrs::AllowNeonARMv8);
668668
} else {
669669
if (Subtarget->hasFPARMv8())
670-
ATS.emitFPU(ARM::FP_ARMV8);
670+
// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
671+
// FPU, but there are two different names for it depending on the CPU.
672+
ATS.emitFPU(Subtarget->hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
671673
else if (Subtarget->hasVFP4())
672674
ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
673675
else if (Subtarget->hasVFP3())

‎llvm/lib/Target/ARM/ARMFPUName.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ ARM_FPU_NAME("vfpv3", VFPV3)
2323
ARM_FPU_NAME("vfpv3-d16", VFPV3_D16)
2424
ARM_FPU_NAME("vfpv4", VFPV4)
2525
ARM_FPU_NAME("vfpv4-d16", VFPV4_D16)
26+
ARM_FPU_NAME("fpv5-d16", FPV5_D16)
2627
ARM_FPU_NAME("fp-armv8", FP_ARMV8)
2728
ARM_FPU_NAME("neon", NEON)
2829
ARM_FPU_NAME("neon-vfpv4", NEON_VFPV4)

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8844,6 +8844,8 @@ static const struct {
88448844
{ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
88458845
{ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
88468846
{ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
8847+
{ARM::FPV5_D16, ARM::FeatureFPARMv8 | ARM::FeatureD16,
8848+
ARM::FeatureNEON | ARM::FeatureCrypto},
88478849
{ARM::FP_ARMV8, ARM::FeatureFPARMv8,
88488850
ARM::FeatureNEON | ARM::FeatureCrypto},
88498851
{ARM::NEON, ARM::FeatureNEON, 0},

‎llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -848,6 +848,14 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
848848
/* OverwriteExisting= */ false);
849849
break;
850850

851+
// FPV5_D16 is identical to FP_ARMV8 except for the number of D registers, so
852+
// uses the FP_ARMV8_D16 build attribute.
853+
case ARM::FPV5_D16:
854+
setAttributeItem(ARMBuildAttrs::FP_arch,
855+
ARMBuildAttrs::AllowFPARMv8B,
856+
/* OverwriteExisting= */ false);
857+
break;
858+
851859
case ARM::NEON:
852860
setAttributeItem(ARMBuildAttrs::FP_arch,
853861
ARMBuildAttrs::AllowFPv3A,

‎llvm/test/CodeGen/ARM/build-attributes.ll

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,9 @@
2626
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3
2727
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
2828
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
29+
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT
30+
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SINGLE
31+
; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-DOUBLE
2932
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
3033
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
3134
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
@@ -410,6 +413,26 @@
410413
; CORTEX-M4-HARD-NOT: .eabi_attribute 44
411414
; CORTEX-M4-HARD-NOT: .eabi_attribute 68
412415

416+
; CORTEX-M7: .cpu cortex-m7
417+
; CORTEX-M7: .eabi_attribute 6, 13
418+
; CORTEX-M7: .eabi_attribute 7, 77
419+
; CORTEX-M7: .eabi_attribute 8, 0
420+
; CORTEX-M7: .eabi_attribute 9, 2
421+
; CORTEX-M7-SOFT-NOT: .fpu
422+
; CORTEX-M7-SINGLE: .fpu fpv5-d16
423+
; CORTEX-M7-DOUBLE: .fpu fpv5-d16
424+
; CORTEX-M7: .eabi_attribute 17, 1
425+
; CORTEX-M7: .eabi_attribute 20, 1
426+
; CORTEX-M7: .eabi_attribute 21, 1
427+
; CORTEX-M7: .eabi_attribute 23, 3
428+
; CORTEX-M7: .eabi_attribute 24, 1
429+
; CORTEX-M7: .eabi_attribute 25, 1
430+
; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
431+
; CORTEX-M7-SINGLE: .eabi_attribute 27, 1
432+
; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
433+
; CORTEX-M7: .eabi_attribute 36, 1
434+
; CORTEX-M7: .eabi_attribute 14, 0
435+
413436
; CORTEX-R5: .cpu cortex-r5
414437
; CORTEX-R5: .eabi_attribute 6, 10
415438
; CORTEX-R5: .eabi_attribute 7, 82

‎llvm/test/CodeGen/Thumb2/cortex-fp.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM3
22
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4
3+
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM7
34
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXA8
45

56

@@ -8,6 +9,7 @@ entry:
89
; CHECK-LABEL: foo:
910
; CORTEXM3: bl ___mulsf3
1011
; CORTEXM4: vmul.f32 s
12+
; CORTEXM7: vmul.f32 s
1113
; CORTEXA8: vmul.f32 d
1214
%0 = fmul float %a, %b
1315
ret float %0
@@ -19,6 +21,7 @@ entry:
1921
%0 = fmul double %a, %b
2022
; CORTEXM3: bl ___muldf3
2123
; CORTEXM4: {{bl|b.w}} ___muldf3
24+
; CORTEXM7: vmul.f64 d
2225
; CORTEXA8: vmul.f64 d
2326
ret double %0
2427
}

‎llvm/test/CodeGen/Thumb2/float-cmp.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
22
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
3+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
34
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
45

56

‎llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
22
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
3-
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
3+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP
4+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON
45

56
declare double @llvm.sqrt.f64(double %Val)
67
define double @sqrt_d(double %a) {
@@ -119,9 +120,11 @@ define double @copysign_d(double %a, double %b) {
119120
; CHECK-LABEL: copysign_d:
120121
; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
121122
; SOFT: bfi r1, [[REG]], #31, #1
122-
; HARD: vmov.i32 [[REG:d[0-9]+]], #0x80000000
123-
; HARD: vshl.i64 [[REG]], [[REG]], #32
124-
; HARD: vbsl [[REG]], d
123+
; VFP: lsrs [[REG:r[0-9]+]], r3, #31
124+
; VFP: bfi r1, [[REG]], #31, #1
125+
; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000
126+
; NEON: vshl.i64 [[REG]], [[REG]], #32
127+
; NEON: vbsl [[REG]], d
125128
%1 = call double @llvm.copysign.f64(double %a, double %b)
126129
ret double %1
127130
}
@@ -185,8 +188,9 @@ define double @fmuladd_d(double %a, double %b, double %c) {
185188
; CHECK-LABEL: fmuladd_d:
186189
; SOFT: bl __aeabi_dmul
187190
; SOFT: bl __aeabi_dadd
188-
; HARD: vmul.f64
189-
; HARD: vadd.f64
191+
; NEON: vmul.f64
192+
; NEON: vadd.f64
193+
; VFP: vmla.f64
190194
%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
191195
ret double %1
192196
}

‎llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
22
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
3-
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
3+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP
4+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON
45

56
declare float @llvm.sqrt.f32(float %Val)
67
define float @sqrt_f(float %a) {
@@ -117,8 +118,10 @@ define float @copysign_f(float %a, float %b) {
117118
; NONE: bfi r{{[0-9]+}}, [[REG]], #31, #1
118119
; SP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
119120
; SP: bfi r{{[0-9]+}}, [[REG]], #31, #1
120-
; DP: vmov.i32 [[REG:d[0-9]+]], #0x80000000
121-
; DP: vbsl [[REG]], d
121+
; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
122+
; VFP: bfi r{{[0-9]+}}, [[REG]], #31, #1
123+
; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000
124+
; NEON: vbsl [[REG]], d
122125
%1 = call float @llvm.copysign.f32(float %a, float %b)
123126
ret float %1
124127
}
@@ -185,8 +188,9 @@ define float @fmuladd_f(float %a, float %b, float %c) {
185188
; SOFT: bl __aeabi_fmul
186189
; SOFT: bl __aeabi_fadd
187190
; SP: vmla.f32
188-
; DP: vmul.f32
189-
; DP: vadd.f32
191+
; VFP: vmla.f32
192+
; NEON: vmul.f32
193+
; NEON: vadd.f32
190194
%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
191195
ret float %1
192196
}

‎llvm/test/CodeGen/Thumb2/float-ops.ll

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
2-
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
3-
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
2+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VFP4-ALL
3+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=FP-ARMv8
4+
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP4-ALL -check-prefix=VFP4-DP
45

56
define float @add_f(float %a, float %b) {
67
entry:
@@ -263,8 +264,9 @@ define float @select_f(float %a, float %b, i1 %c) {
263264
; NONE: tst.w r2, #1
264265
; NONE: moveq r0, r1
265266
; HARD: tst.w r0, #1
266-
; HARD: vmovne.f32 s1, s0
267-
; HARD: vmov.f32 s0, s1
267+
; VFP4-ALL: vmovne.f32 s1, s0
268+
; VFP4-ALL: vmov.f32 s0, s1
269+
; FP-ARMv8: vseleq.f32 s0, s1, s0
268270
%1 = select i1 %c, float %a, float %b
269271
ret float %1
270272
}
@@ -283,8 +285,9 @@ define double @select_d(double %a, double %b, i1 %c) {
283285
; SP-DAG: movne [[BHI]], [[AHI]]
284286
; SP: vmov d0, [[BLO]], [[BHI]]
285287
; DP: tst.w r0, #1
286-
; DP: vmovne.f64 d1, d0
287-
; DP: vmov.f64 d0, d1
288+
; VFP4-DP: vmovne.f64 d1, d0
289+
; VFP4-DP: vmov.f64 d0, d1
290+
; FP-ARMV8: vseleq.f64 d0, d1, d0
288291
%1 = select i1 %c, double %a, double %b
289292
ret double %1
290293
}

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