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Test cases for vscale immediates
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‎llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt -S -loop-reduce < %s | FileCheck %s
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;;target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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define void @mulvl123_addressing(ptr %src, ptr %dst, i64 %count) #0 {
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; CHECK-LABEL: define void @mulvl123_addressing(
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; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i64 [[COUNT:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[VSCALE]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = mul nuw nsw i64 [[VSCALE]], 48
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; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i64 [[VSCALE]], 80
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i64 [[VSCALE]], 5
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP:%.*]], [[FOR_BODY]] ], [ [[SRC]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IDX_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 16 x i8>, ptr [[LSR_IV]], align 16
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; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP6:%.*]] = load <vscale x 16 x i8>, ptr [[SCEVGEP3]], align 16
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; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP3]]
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; CHECK-NEXT: [[TMP7:%.*]] = load <vscale x 16 x i8>, ptr [[SCEVGEP2]], align 16
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP2]]
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; CHECK-NEXT: [[TMP8:%.*]] = load <vscale x 16 x i8>, ptr [[SCEVGEP1]], align 16
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; CHECK-NEXT: [[TMP9:%.*]] = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> [[TMP5]], <vscale x 16 x i8> [[TMP6]])
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; CHECK-NEXT: [[TMP10:%.*]] = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> [[TMP7]], <vscale x 16 x i8> [[TMP8]])
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; CHECK-NEXT: [[TMP11:%.*]] = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]])
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; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[IDX]]
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; CHECK-NEXT: store <vscale x 16 x i8> [[TMP11]], ptr [[ARRAYIDX4]], align 16
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; CHECK-NEXT: [[IDX_NEXT]] = add i64 [[IDX]], [[TMP0]]
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; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP1]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX_NEXT]], [[COUNT]]
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_EXIT:%.*]]
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; CHECK: for.exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%vscale = tail call i64 @llvm.vscale.i64()
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%2 = shl nuw nsw i64 %vscale, 4
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%mul = shl nuw nsw i64 %vscale, 6
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br label %for.body
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for.body:
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%src.addr = phi ptr [ %src, %entry ], [ %src.addr.next, %for.body ]
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%idx = phi i64 [ 0, %entry ], [ %idx.next, %for.body ]
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%arrayidx = getelementptr inbounds i8, ptr %src.addr, i64 %idx
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%3 = load <vscale x 16 x i8>, ptr %arrayidx
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%4 = getelementptr <vscale x 16 x i8>, ptr %arrayidx, i64 1
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%5 = load <vscale x 16 x i8>, ptr %4
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%6 = getelementptr <vscale x 16 x i8>, ptr %arrayidx, i64 2
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%7 = load <vscale x 16 x i8>, ptr %6
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%8 = getelementptr <vscale x 16 x i8>, ptr %arrayidx, i64 3
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%9 = load <vscale x 16 x i8>, ptr %8
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%10 = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %5)
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%11 = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> %7, <vscale x 16 x i8> %9)
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%12 = tail call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> %10, <vscale x 16 x i8> %11)
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%src.addr.next = getelementptr inbounds i8, ptr %src.addr, i64 %mul
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%arrayidx4 = getelementptr inbounds i8, ptr %dst, i64 %idx
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store <vscale x 16 x i8> %12, ptr %arrayidx4
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%idx.next = add i64 %idx, %2
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%cmp = icmp ult i64 %idx.next, %count
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br i1 %cmp, label %for.body, label %for.exit
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for.exit:
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ret void
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}
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define void @many_mulvl1_addressing(ptr %src_rows, ptr %dst_rows, i64 %stride, i64 %count) #0 {
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; CHECK-LABEL: define void @many_mulvl1_addressing(
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; CHECK-SAME: ptr [[SRC_ROWS:%.*]], ptr [[DST_ROWS:%.*]], i64 [[STRIDE:%.*]], i64 [[COUNT:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[MUL:%.*]] = shl i64 [[VSCALE]], 5
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; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[VSCALE]], 4
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC_ROWS]], i64 [[STRIDE]]
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP0]]
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; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[SRC_ROWS]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[VSCALE]], 3
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; CHECK-NEXT: [[SCEVGEP7:%.*]] = getelementptr i8, ptr [[DST_ROWS]], i64 [[TMP1]]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[LSR_IV10:%.*]] = phi i64 [ [[LSR_IV_NEXT11:%.*]], [[FOR_BODY]] ], [ [[COUNT]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
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; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[SRC_ROWS]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[DST_ROWS]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[TMP2:%.*]] = load <vscale x 16 x i8>, ptr [[SCEVGEP6]], align 16
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; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[SCEVGEP4]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[TMP3:%.*]] = load <vscale x 16 x i8>, ptr [[SCEVGEP5]], align 16
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; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[TMP4:%.*]] = load <vscale x 16 x i8>, ptr [[SCEVGEP3]], align 16
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; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 16 x i8>, ptr [[SCEVGEP2]], align 16
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; CHECK-NEXT: [[TMP6:%.*]] = add <vscale x 16 x i8> [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = add <vscale x 16 x i8> [[TMP3]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = bitcast <vscale x 16 x i8> [[TMP6]] to <vscale x 8 x i16>
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; CHECK-NEXT: [[TMP9:%.*]] = trunc <vscale x 8 x i16> [[TMP8]] to <vscale x 8 x i8>
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; CHECK-NEXT: store <vscale x 8 x i8> [[TMP9]], ptr [[SCEVGEP9]], align 8
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; CHECK-NEXT: [[TMP10:%.*]] = bitcast <vscale x 16 x i8> [[TMP7]] to <vscale x 8 x i16>
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; CHECK-NEXT: [[SCEVGEP8:%.*]] = getelementptr i8, ptr [[SCEVGEP7]], i64 [[LSR_IV]]
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; CHECK-NEXT: [[TMP11:%.*]] = trunc <vscale x 8 x i16> [[TMP10]] to <vscale x 8 x i8>
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; CHECK-NEXT: store <vscale x 8 x i8> [[TMP11]], ptr [[SCEVGEP8]], align 8
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], [[MUL]]
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; CHECK-NEXT: [[LSR_IV_NEXT11]] = add i64 [[LSR_IV10]], -1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[LSR_IV_NEXT11]], 0
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_EXIT:%.*]], label [[FOR_BODY]]
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; CHECK: for.exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%vscale = tail call i64 @llvm.vscale.i64()
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%mul = shl nuw nsw i64 %vscale, 5
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br label %for.body
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for.body:
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%src_row_addr = phi ptr [ %src_rows, %entry ], [ %add_ptr_src, %for.body ]
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%dst_row_addr = phi ptr [ %dst_rows, %entry ], [ %add_ptr_dst, %for.body ]
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%idx = phi i64 [ 0, %entry ], [ %inc, %for.body ]
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%2 = load <vscale x 16 x i8>, ptr %src_row_addr
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%3 = getelementptr <vscale x 16 x i8>, ptr %src_row_addr, i64 1
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%4 = load <vscale x 16 x i8>, ptr %3
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%arrayidx2 = getelementptr inbounds i8, ptr %src_row_addr, i64 %stride
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%5 = load <vscale x 16 x i8>, ptr %arrayidx2
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%6 = getelementptr <vscale x 16 x i8>, ptr %arrayidx2, i64 1
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%7 = load <vscale x 16 x i8>, ptr %6
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%8 = add <vscale x 16 x i8> %2, %5
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%9 = add <vscale x 16 x i8> %4, %7
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%10 = bitcast <vscale x 16 x i8> %8 to <vscale x 8 x i16>
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%11 = trunc <vscale x 8 x i16> %10 to <vscale x 8 x i8>
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store <vscale x 8 x i8> %11, ptr %dst_row_addr
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%12 = bitcast <vscale x 16 x i8> %9 to <vscale x 8 x i16>
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%13 = getelementptr <vscale x 8 x i8>, ptr %dst_row_addr, i64 1
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%14 = trunc <vscale x 8 x i16> %12 to <vscale x 8 x i8>
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store <vscale x 8 x i8> %14, ptr %13
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%add_ptr_src = getelementptr inbounds i8, ptr %src_row_addr, i64 %mul
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%add_ptr_dst = getelementptr inbounds i8, ptr %dst_row_addr, i64 %mul
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%inc = add nuw i64 %idx, 1
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%exitcond = icmp eq i64 %inc, %count
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br i1 %exitcond, label %for.exit, label %for.body
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for.exit:
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ret void
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}
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attributes #0 = { "target-features"="+sve2" vscale_range(1,16) }

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