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Leon Clark
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[AMDGPU] Use LSH for lowering ctlz_zero_undef.i8/i16
1 parent c52b18d commit 38904da

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2 files changed

+52
-44
lines changed

2 files changed

+52
-44
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3081,20 +3081,29 @@ static bool isCttzOpc(unsigned Opc) {
30813081
SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
30823082
SelectionDAG &DAG) const {
30833083
auto SL = SDLoc(Op);
3084+
auto Opc = Op.getOpcode();
30843085
auto Arg = Op.getOperand(0u);
30853086
auto ResultVT = Op.getValueType();
30863087

30873088
if (ResultVT != MVT::i8 && ResultVT != MVT::i16)
30883089
return {};
30893090

3090-
assert(isCtlzOpc(Op.getOpcode()));
3091+
assert(isCtlzOpc(Opc));
30913092
assert(ResultVT == Arg.getValueType());
30923093

3093-
auto const LeadingZeroes = 32u - ResultVT.getFixedSizeInBits();
3094-
auto SubVal = DAG.getConstant(LeadingZeroes, SL, MVT::i32);
3094+
auto const NumBits = ResultVT.getFixedSizeInBits();
3095+
auto NumExtBits = DAG.getConstant(32u - NumBits, SL, MVT::i32);
30953096
auto NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg);
3096-
NewOp = DAG.getNode(Op.getOpcode(), SL, MVT::i32, NewOp);
3097-
NewOp = DAG.getNode(ISD::SUB, SL, MVT::i32, NewOp, SubVal);
3097+
3098+
if (Opc == ISD::CTLZ_ZERO_UNDEF) {
3099+
NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, NumExtBits);
3100+
NewOp = DAG.getNode(Opc, SL, MVT::i32, NewOp);
3101+
}
3102+
else {
3103+
NewOp = DAG.getNode(Opc, SL, MVT::i32, NewOp);
3104+
NewOp = DAG.getNode(ISD::SUB, SL, MVT::i32, NewOp, NumExtBits);
3105+
}
3106+
30983107
return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp);
30993108
}
31003109

‎llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll

Lines changed: 38 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -314,9 +314,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
314314
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
315315
; SI-NEXT: s_mov_b32 s3, 0xf000
316316
; SI-NEXT: s_waitcnt lgkmcnt(0)
317-
; SI-NEXT: s_and_b32 s2, s2, 0xff
318-
; SI-NEXT: s_flbit_i32_b32 s2, s2
319-
; SI-NEXT: s_sub_i32 s4, s2, 24
317+
; SI-NEXT: s_lshl_b32 s2, s2, 24
318+
; SI-NEXT: s_flbit_i32_b32 s4, s2
320319
; SI-NEXT: s_mov_b32 s2, -1
321320
; SI-NEXT: v_mov_b32_e32 v0, s4
322321
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -327,9 +326,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
327326
; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
328327
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
329328
; VI-NEXT: s_waitcnt lgkmcnt(0)
330-
; VI-NEXT: s_and_b32 s2, s2, 0xff
329+
; VI-NEXT: s_lshl_b32 s2, s2, 24
331330
; VI-NEXT: s_flbit_i32_b32 s2, s2
332-
; VI-NEXT: s_sub_i32 s2, s2, 24
333331
; VI-NEXT: v_mov_b32_e32 v0, s0
334332
; VI-NEXT: v_mov_b32_e32 v1, s1
335333
; VI-NEXT: v_mov_b32_e32 v2, s2
@@ -349,13 +347,13 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
349347
; EG-NEXT: ALU clause starting at 8:
350348
; EG-NEXT: MOV * T0.X, 0.0,
351349
; EG-NEXT: ALU clause starting at 9:
352-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
350+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
351+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
352+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
353353
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
354354
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
355-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
356-
; EG-NEXT: -24(nan), 0(0.000000e+00)
357355
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
358-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
356+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
359357
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
360358
; EG-NEXT: LSHL T0.X, PV.W, PS,
361359
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -391,9 +389,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
391389
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
392390
; SI-NEXT: s_mov_b32 s3, 0xf000
393391
; SI-NEXT: s_waitcnt lgkmcnt(0)
394-
; SI-NEXT: s_and_b32 s2, s2, 0xffff
395-
; SI-NEXT: s_flbit_i32_b32 s2, s2
396-
; SI-NEXT: s_add_i32 s4, s2, -16
392+
; SI-NEXT: s_lshl_b32 s2, s2, 16
393+
; SI-NEXT: s_flbit_i32_b32 s4, s2
397394
; SI-NEXT: s_mov_b32 s2, -1
398395
; SI-NEXT: v_mov_b32_e32 v0, s4
399396
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
@@ -426,13 +423,13 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
426423
; EG-NEXT: ALU clause starting at 8:
427424
; EG-NEXT: MOV * T0.X, 0.0,
428425
; EG-NEXT: ALU clause starting at 9:
429-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
426+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
427+
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
428+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
430429
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
431430
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
432-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
433-
; EG-NEXT: -16(nan), 0(0.000000e+00)
434431
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
435-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
432+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
436433
; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
437434
; EG-NEXT: LSHL T0.X, PV.W, PS,
438435
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -590,8 +587,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
590587
; SI-NEXT: s_mov_b32 s4, s0
591588
; SI-NEXT: s_mov_b32 s5, s1
592589
; SI-NEXT: s_waitcnt vmcnt(0)
593-
; SI-NEXT: v_ffbh_u32_e32 v1, v0
594-
; SI-NEXT: v_subrev_i32_e32 v1, vcc, 24, v1
590+
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
591+
; SI-NEXT: v_ffbh_u32_e32 v1, v1
595592
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
596593
; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc
597594
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
@@ -605,8 +602,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
605602
; VI-NEXT: v_mov_b32_e32 v1, s3
606603
; VI-NEXT: flat_load_ubyte v0, v[0:1]
607604
; VI-NEXT: s_waitcnt vmcnt(0)
608-
; VI-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
609-
; VI-NEXT: v_subrev_u32_e32 v1, vcc, 24, v1
605+
; VI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
606+
; VI-NEXT: v_ffbh_u32_e32 v1, v1
610607
; VI-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
611608
; VI-NEXT: v_cndmask_b32_e32 v2, 32, v1, vcc
612609
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -618,7 +615,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
618615
; EG: ; %bb.0:
619616
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
620617
; EG-NEXT: TEX 0 @6
621-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
618+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
622619
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
623620
; EG-NEXT: CF_END
624621
; EG-NEXT: PAD
@@ -627,10 +624,11 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
627624
; EG-NEXT: ALU clause starting at 8:
628625
; EG-NEXT: MOV * T0.X, KC0[2].Z,
629626
; EG-NEXT: ALU clause starting at 9:
630-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
631-
; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,
632-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
633-
; EG-NEXT: -24(nan), 3(4.203895e-45)
627+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
628+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
629+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
630+
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
631+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
634632
; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,
635633
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
636634
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
@@ -685,8 +683,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
685683
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
686684
; SI-NEXT: s_waitcnt vmcnt(0)
687685
; SI-NEXT: v_or_b32_e32 v0, v0, v1
688-
; SI-NEXT: v_ffbh_u32_e32 v1, v0
689-
; SI-NEXT: v_add_i32_e32 v1, vcc, -16, v1
686+
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
687+
; SI-NEXT: v_ffbh_u32_e32 v1, v1
690688
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
691689
; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc
692690
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
@@ -721,7 +719,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
721719
; EG: ; %bb.0:
722720
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
723721
; EG-NEXT: TEX 0 @6
724-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
722+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
725723
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
726724
; EG-NEXT: CF_END
727725
; EG-NEXT: PAD
@@ -730,10 +728,11 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
730728
; EG-NEXT: ALU clause starting at 8:
731729
; EG-NEXT: MOV * T0.X, KC0[2].Z,
732730
; EG-NEXT: ALU clause starting at 9:
733-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
734-
; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,
735-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
736-
; EG-NEXT: -16(nan), 3(4.203895e-45)
731+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
732+
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
733+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
734+
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
735+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
737736
; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,
738737
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
739738
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
@@ -1102,8 +1101,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11021101
; SI-NEXT: s_mov_b32 s4, s0
11031102
; SI-NEXT: s_mov_b32 s5, s1
11041103
; SI-NEXT: s_waitcnt vmcnt(0)
1104+
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
11051105
; SI-NEXT: v_ffbh_u32_e32 v0, v0
1106-
; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0
11071106
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
11081107
; SI-NEXT: s_endpgm
11091108
;
@@ -1116,8 +1115,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11161115
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
11171116
; VI-NEXT: flat_load_ubyte v0, v[0:1]
11181117
; VI-NEXT: s_waitcnt vmcnt(0)
1119-
; VI-NEXT: v_ffbh_u32_e32 v0, v0
1120-
; VI-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
1118+
; VI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
1119+
; VI-NEXT: v_ffbh_u32_e32 v2, v0
11211120
; VI-NEXT: v_mov_b32_e32 v0, s0
11221121
; VI-NEXT: v_mov_b32_e32 v1, s1
11231122
; VI-NEXT: flat_store_byte v[0:1], v2
@@ -1136,13 +1135,13 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11361135
; EG-NEXT: ALU clause starting at 8:
11371136
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,
11381137
; EG-NEXT: ALU clause starting at 9:
1139-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
1138+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
1139+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
1140+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
11401141
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
11411142
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
1142-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
1143-
; EG-NEXT: -24(nan), 0(0.000000e+00)
11441143
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
1145-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
1144+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
11461145
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
11471146
; EG-NEXT: LSHL T0.X, PV.W, PS,
11481147
; EG-NEXT: LSHL * T0.W, literal.x, PS,

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