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michaelmaitlandmichaelmaitland
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[RISCV][GISel] First mask argument placed in v0 according to RISCV Ve… (#79343)
…ctor CC.
1 parent 6e4930c commit 3967510

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3 files changed

+138
-60
lines changed

3 files changed

+138
-60
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

Lines changed: 22 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,9 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
3434
// Whether this is assigning args for a return.
3535
bool IsRet;
3636

37+
// true if assignArg has been called for a mask argument, false otherwise.
38+
bool AssignedFirstMaskArg = false;
39+
3740
public:
3841
RISCVOutgoingValueAssigner(
3942
RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
@@ -48,10 +51,16 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
4851
const DataLayout &DL = MF.getDataLayout();
4952
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
5053

54+
std::optional<unsigned> FirstMaskArgument;
55+
if (Subtarget.hasVInstructions() && !AssignedFirstMaskArg &&
56+
ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1) {
57+
FirstMaskArgument = ValNo;
58+
AssignedFirstMaskArg = true;
59+
}
60+
5161
if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
5262
LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty,
53-
*Subtarget.getTargetLowering(),
54-
/*FirstMaskArgument=*/std::nullopt))
63+
*Subtarget.getTargetLowering(), FirstMaskArgument))
5564
return true;
5665

5766
StackSize = State.getStackSize();
@@ -172,6 +181,9 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
172181
// Whether this is assigning args from a return.
173182
bool IsRet;
174183

184+
// true if assignArg has been called for a mask argument, false otherwise.
185+
bool AssignedFirstMaskArg = false;
186+
175187
public:
176188
RISCVIncomingValueAssigner(
177189
RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
@@ -189,10 +201,16 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
189201
if (LocVT.isScalableVector())
190202
MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
191203

204+
std::optional<unsigned> FirstMaskArgument;
205+
if (Subtarget.hasVInstructions() && !AssignedFirstMaskArg &&
206+
ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1) {
207+
FirstMaskArgument = ValNo;
208+
AssignedFirstMaskArg = true;
209+
}
210+
192211
if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
193212
LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty,
194-
*Subtarget.getTargetLowering(),
195-
/*FirstMaskArgument=*/std::nullopt))
213+
*Subtarget.getTargetLowering(), FirstMaskArgument))
196214
return true;
197215

198216
StackSize = State.getStackSize();

‎llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll

Lines changed: 88 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -407,16 +407,16 @@ entry:
407407
define void @test_args_nxv64i1(<vscale x 64 x i1> %a) {
408408
; RV32-LABEL: name: test_args_nxv64i1
409409
; RV32: bb.1.entry:
410-
; RV32-NEXT: liveins: $v8
410+
; RV32-NEXT: liveins: $v0
411411
; RV32-NEXT: {{ $}}
412-
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8
412+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0
413413
; RV32-NEXT: PseudoRET
414414
;
415415
; RV64-LABEL: name: test_args_nxv64i1
416416
; RV64: bb.1.entry:
417-
; RV64-NEXT: liveins: $v8
417+
; RV64-NEXT: liveins: $v0
418418
; RV64-NEXT: {{ $}}
419-
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8
419+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0
420420
; RV64-NEXT: PseudoRET
421421
entry:
422422
ret void
@@ -425,16 +425,16 @@ entry:
425425
define void @test_args_nxv32i1(<vscale x 32 x i1> %a) {
426426
; RV32-LABEL: name: test_args_nxv32i1
427427
; RV32: bb.1.entry:
428-
; RV32-NEXT: liveins: $v8
428+
; RV32-NEXT: liveins: $v0
429429
; RV32-NEXT: {{ $}}
430-
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8
430+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0
431431
; RV32-NEXT: PseudoRET
432432
;
433433
; RV64-LABEL: name: test_args_nxv32i1
434434
; RV64: bb.1.entry:
435-
; RV64-NEXT: liveins: $v8
435+
; RV64-NEXT: liveins: $v0
436436
; RV64-NEXT: {{ $}}
437-
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8
437+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0
438438
; RV64-NEXT: PseudoRET
439439
entry:
440440
ret void
@@ -443,16 +443,16 @@ entry:
443443
define void @test_args_nxv16i1(<vscale x 16 x i1> %a) {
444444
; RV32-LABEL: name: test_args_nxv16i1
445445
; RV32: bb.1.entry:
446-
; RV32-NEXT: liveins: $v8
446+
; RV32-NEXT: liveins: $v0
447447
; RV32-NEXT: {{ $}}
448-
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8
448+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0
449449
; RV32-NEXT: PseudoRET
450450
;
451451
; RV64-LABEL: name: test_args_nxv16i1
452452
; RV64: bb.1.entry:
453-
; RV64-NEXT: liveins: $v8
453+
; RV64-NEXT: liveins: $v0
454454
; RV64-NEXT: {{ $}}
455-
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8
455+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0
456456
; RV64-NEXT: PseudoRET
457457
entry:
458458
ret void
@@ -461,16 +461,16 @@ entry:
461461
define void @test_args_nxv8i1(<vscale x 8 x i1> %a) {
462462
; RV32-LABEL: name: test_args_nxv8i1
463463
; RV32: bb.1.entry:
464-
; RV32-NEXT: liveins: $v8
464+
; RV32-NEXT: liveins: $v0
465465
; RV32-NEXT: {{ $}}
466-
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8
466+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0
467467
; RV32-NEXT: PseudoRET
468468
;
469469
; RV64-LABEL: name: test_args_nxv8i1
470470
; RV64: bb.1.entry:
471-
; RV64-NEXT: liveins: $v8
471+
; RV64-NEXT: liveins: $v0
472472
; RV64-NEXT: {{ $}}
473-
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8
473+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0
474474
; RV64-NEXT: PseudoRET
475475
entry:
476476
ret void
@@ -479,16 +479,16 @@ entry:
479479
define void @test_args_nxv4i1(<vscale x 4 x i1> %a) {
480480
; RV32-LABEL: name: test_args_nxv4i1
481481
; RV32: bb.1.entry:
482-
; RV32-NEXT: liveins: $v8
482+
; RV32-NEXT: liveins: $v0
483483
; RV32-NEXT: {{ $}}
484-
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8
484+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
485485
; RV32-NEXT: PseudoRET
486486
;
487487
; RV64-LABEL: name: test_args_nxv4i1
488488
; RV64: bb.1.entry:
489-
; RV64-NEXT: liveins: $v8
489+
; RV64-NEXT: liveins: $v0
490490
; RV64-NEXT: {{ $}}
491-
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8
491+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
492492
; RV64-NEXT: PseudoRET
493493
entry:
494494
ret void
@@ -497,16 +497,16 @@ entry:
497497
define void @test_args_nxv2i1(<vscale x 2 x i1> %a) {
498498
; RV32-LABEL: name: test_args_nxv2i1
499499
; RV32: bb.1.entry:
500-
; RV32-NEXT: liveins: $v8
500+
; RV32-NEXT: liveins: $v0
501501
; RV32-NEXT: {{ $}}
502-
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
502+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0
503503
; RV32-NEXT: PseudoRET
504504
;
505505
; RV64-LABEL: name: test_args_nxv2i1
506506
; RV64: bb.1.entry:
507-
; RV64-NEXT: liveins: $v8
507+
; RV64-NEXT: liveins: $v0
508508
; RV64-NEXT: {{ $}}
509-
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
509+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0
510510
; RV64-NEXT: PseudoRET
511511
entry:
512512
ret void
@@ -515,16 +515,16 @@ entry:
515515
define void @test_args_nxv1i1(<vscale x 1 x i1> %a) {
516516
; RV32-LABEL: name: test_args_nxv1i1
517517
; RV32: bb.1.entry:
518-
; RV32-NEXT: liveins: $v8
518+
; RV32-NEXT: liveins: $v0
519519
; RV32-NEXT: {{ $}}
520-
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
520+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
521521
; RV32-NEXT: PseudoRET
522522
;
523523
; RV64-LABEL: name: test_args_nxv1i1
524524
; RV64: bb.1.entry:
525-
; RV64-NEXT: liveins: $v8
525+
; RV64-NEXT: liveins: $v0
526526
; RV64-NEXT: {{ $}}
527-
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
527+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
528528
; RV64-NEXT: PseudoRET
529529
entry:
530530
ret void
@@ -907,3 +907,63 @@ define void @test_args_nxv32b16(<vscale x 32 x bfloat> %a) {
907907
entry:
908908
ret void
909909
}
910+
911+
define void @test_args_nxv1i1_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
912+
; RV32-LABEL: name: test_args_nxv1i1_nxv1i1
913+
; RV32: bb.1.entry:
914+
; RV32-NEXT: liveins: $v0, $v8
915+
; RV32-NEXT: {{ $}}
916+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
917+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
918+
; RV32-NEXT: PseudoRET
919+
;
920+
; RV64-LABEL: name: test_args_nxv1i1_nxv1i1
921+
; RV64: bb.1.entry:
922+
; RV64-NEXT: liveins: $v0, $v8
923+
; RV64-NEXT: {{ $}}
924+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
925+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
926+
; RV64-NEXT: PseudoRET
927+
entry:
928+
ret void
929+
}
930+
931+
define void @test_args_nxv1i1_nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b) {
932+
; RV32-LABEL: name: test_args_nxv1i1_nxv1i32
933+
; RV32: bb.1.entry:
934+
; RV32-NEXT: liveins: $v0, $v8
935+
; RV32-NEXT: {{ $}}
936+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
937+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
938+
; RV32-NEXT: PseudoRET
939+
;
940+
; RV64-LABEL: name: test_args_nxv1i1_nxv1i32
941+
; RV64: bb.1.entry:
942+
; RV64-NEXT: liveins: $v0, $v8
943+
; RV64-NEXT: {{ $}}
944+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
945+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
946+
; RV64-NEXT: PseudoRET
947+
entry:
948+
ret void
949+
}
950+
951+
define void @test_args_nxv1i32_nxv1i1(<vscale x 1 x i32> %a, <vscale x 1 x i1> %b) {
952+
; RV32-LABEL: name: test_args_nxv1i32_nxv1i1
953+
; RV32: bb.1.entry:
954+
; RV32-NEXT: liveins: $v0, $v8
955+
; RV32-NEXT: {{ $}}
956+
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
957+
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
958+
; RV32-NEXT: PseudoRET
959+
;
960+
; RV64-LABEL: name: test_args_nxv1i32_nxv1i1
961+
; RV64: bb.1.entry:
962+
; RV64-NEXT: liveins: $v0, $v8
963+
; RV64-NEXT: {{ $}}
964+
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
965+
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
966+
; RV64-NEXT: PseudoRET
967+
entry:
968+
ret void
969+
}

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