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[X86] Support lowering of FMINIMUMNUM/FMAXIMUMNUM
1 parent 0965515 commit 398068e

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6 files changed

+2931
-125
lines changed

6 files changed

+2931
-125
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -402,6 +402,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
402402
case ISD::FMAXNUM_IEEE:
403403
case ISD::FMINIMUM:
404404
case ISD::FMAXIMUM:
405+
case ISD::FMINIMUMNUM:
406+
case ISD::FMAXIMUMNUM:
405407
case ISD::FCOPYSIGN:
406408
case ISD::FSQRT:
407409
case ISD::FSIN:
@@ -1081,6 +1083,13 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
10811083
case ISD::FMAXIMUM:
10821084
Results.push_back(TLI.expandFMINIMUM_FMAXIMUM(Node, DAG));
10831085
return;
1086+
case ISD::FMINIMUMNUM:
1087+
case ISD::FMAXIMUMNUM:
1088+
if (SDValue Expanded = TLI.expandFMINIMUMNUM_FMAXIMUMNUM(Node, DAG)) {
1089+
Results.push_back(Expanded);
1090+
return;
1091+
}
1092+
break;
10841093
case ISD::SMIN:
10851094
case ISD::SMAX:
10861095
case ISD::UMIN:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,8 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
149149
case ISD::FMAXNUM_IEEE:
150150
case ISD::FMINIMUM:
151151
case ISD::FMAXIMUM:
152+
case ISD::FMINIMUMNUM:
153+
case ISD::FMAXIMUMNUM:
152154
case ISD::FLDEXP:
153155
case ISD::ABDS:
154156
case ISD::ABDU:

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 35 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -623,6 +623,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
623623
setOperationAction(ISD::FMAXNUM, VT, Action);
624624
setOperationAction(ISD::FMINIMUM, VT, Action);
625625
setOperationAction(ISD::FMAXIMUM, VT, Action);
626+
setOperationAction(ISD::FMINIMUMNUM, VT, Action);
627+
setOperationAction(ISD::FMAXIMUMNUM, VT, Action);
626628
setOperationAction(ISD::FSIN, VT, Action);
627629
setOperationAction(ISD::FCOS, VT, Action);
628630
setOperationAction(ISD::FSINCOS, VT, Action);
@@ -1066,6 +1068,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
10661068

10671069
setOperationAction(ISD::FMAXIMUM, MVT::f32, Custom);
10681070
setOperationAction(ISD::FMINIMUM, MVT::f32, Custom);
1071+
setOperationAction(ISD::FMAXIMUMNUM, MVT::f32, Custom);
1072+
setOperationAction(ISD::FMINIMUMNUM, MVT::f32, Custom);
10691073

10701074
setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
10711075
setOperationAction(ISD::FABS, MVT::v4f32, Custom);
@@ -1108,6 +1112,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
11081112
for (auto VT : { MVT::f64, MVT::v4f32, MVT::v2f64 }) {
11091113
setOperationAction(ISD::FMAXIMUM, VT, Custom);
11101114
setOperationAction(ISD::FMINIMUM, VT, Custom);
1115+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
1116+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
11111117
}
11121118

11131119
for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
@@ -1473,6 +1479,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
14731479

14741480
setOperationAction(ISD::FMAXIMUM, VT, Custom);
14751481
setOperationAction(ISD::FMINIMUM, VT, Custom);
1482+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
1483+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
14761484
setOperationAction(ISD::FCANONICALIZE, VT, Custom);
14771485
}
14781486

@@ -1818,6 +1826,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
18181826
for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
18191827
setOperationAction(ISD::FMAXIMUM, VT, Custom);
18201828
setOperationAction(ISD::FMINIMUM, VT, Custom);
1829+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
1830+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
18211831
setOperationAction(ISD::FNEG, VT, Custom);
18221832
setOperationAction(ISD::FABS, VT, Custom);
18231833
setOperationAction(ISD::FMA, VT, Legal);
@@ -2289,6 +2299,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
22892299
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
22902300
setOperationAction(ISD::FMAXIMUM, MVT::f16, Custom);
22912301
setOperationAction(ISD::FMINIMUM, MVT::f16, Custom);
2302+
setOperationAction(ISD::FMAXIMUMNUM, MVT::f16, Custom);
2303+
setOperationAction(ISD::FMINIMUMNUM, MVT::f16, Custom);
22922304
setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
22932305
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
22942306

@@ -2336,6 +2348,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
23362348

23372349
setOperationAction(ISD::FMINIMUM, MVT::v32f16, Custom);
23382350
setOperationAction(ISD::FMAXIMUM, MVT::v32f16, Custom);
2351+
setOperationAction(ISD::FMINIMUMNUM, MVT::v32f16, Custom);
2352+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v32f16, Custom);
23392353
}
23402354

23412355
if (Subtarget.hasVLX()) {
@@ -2383,9 +2397,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
23832397

23842398
setOperationAction(ISD::FMINIMUM, MVT::v8f16, Custom);
23852399
setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Custom);
2400+
setOperationAction(ISD::FMINIMUMNUM, MVT::v8f16, Custom);
2401+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v8f16, Custom);
23862402

23872403
setOperationAction(ISD::FMINIMUM, MVT::v16f16, Custom);
23882404
setOperationAction(ISD::FMAXIMUM, MVT::v16f16, Custom);
2405+
setOperationAction(ISD::FMINIMUMNUM, MVT::v16f16, Custom);
2406+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v16f16, Custom);
23892407
}
23902408
}
23912409

@@ -2444,6 +2462,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
24442462
setOperationAction(ISD::SETCC, VT, Custom);
24452463
setOperationAction(ISD::FMINIMUM, VT, Custom);
24462464
setOperationAction(ISD::FMAXIMUM, VT, Custom);
2465+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
2466+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
24472467
}
24482468
if (Subtarget.hasAVX10_2_512()) {
24492469
setOperationAction(ISD::FADD, MVT::v32bf16, Legal);
@@ -2455,6 +2475,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
24552475
setOperationAction(ISD::SETCC, MVT::v32bf16, Custom);
24562476
setOperationAction(ISD::FMINIMUM, MVT::v32bf16, Custom);
24572477
setOperationAction(ISD::FMAXIMUM, MVT::v32bf16, Custom);
2478+
setOperationAction(ISD::FMINIMUMNUM, MVT::v32bf16, Custom);
2479+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v32bf16, Custom);
24582480
}
24592481
for (auto VT : {MVT::f16, MVT::f32, MVT::f64}) {
24602482
setCondCodeAction(ISD::SETOEQ, VT, Custom);
@@ -28839,13 +28861,15 @@ static SDValue LowerMINMAX(SDValue Op, const X86Subtarget &Subtarget,
2883928861

2884028862
static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2884128863
SelectionDAG &DAG) {
28842-
assert((Op.getOpcode() == ISD::FMAXIMUM || Op.getOpcode() == ISD::FMINIMUM) &&
28843-
"Expected FMAXIMUM or FMINIMUM opcode");
2884428864
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2884528865
EVT VT = Op.getValueType();
2884628866
SDValue X = Op.getOperand(0);
2884728867
SDValue Y = Op.getOperand(1);
2884828868
SDLoc DL(Op);
28869+
bool IsMaxOp =
28870+
Op.getOpcode() == ISD::FMAXIMUM || Op.getOpcode() == ISD::FMAXIMUMNUM;
28871+
bool IsNum =
28872+
Op.getOpcode() == ISD::FMINIMUMNUM || Op.getOpcode() == ISD::FMAXIMUMNUM;
2884928873
if (Subtarget.hasAVX10_2() && TLI.isTypeLegal(VT)) {
2885028874
unsigned Opc = 0;
2885128875
if (VT.isVector())
@@ -28855,7 +28879,7 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2885528879

2885628880
if (Opc) {
2885728881
SDValue Imm =
28858-
DAG.getTargetConstant(Op.getOpcode() == ISD::FMAXIMUM, DL, MVT::i32);
28882+
DAG.getTargetConstant(IsMaxOp + (IsNum ? 16 : 0), DL, MVT::i32);
2885928883
return DAG.getNode(Opc, DL, VT, X, Y, Imm, Op->getFlags());
2886028884
}
2886128885
}
@@ -28865,7 +28889,7 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2886528889
APInt OppositeZero = PreferredZero;
2886628890
EVT IVT = VT.changeTypeToInteger();
2886728891
X86ISD::NodeType MinMaxOp;
28868-
if (Op.getOpcode() == ISD::FMAXIMUM) {
28892+
if (IsMaxOp) {
2886928893
MinMaxOp = X86ISD::FMAX;
2887028894
OppositeZero.setSignBit();
2887128895
} else {
@@ -28995,7 +29019,9 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2899529019
if (IgnoreNaN || DAG.isKnownNeverNaN(NewX))
2899629020
return MinMax;
2899729021

28998-
SDValue IsNaN = DAG.getSetCC(DL, SetCCType, NewX, NewX, ISD::SETUO);
29022+
SDValue IsNaN =
29023+
DAG.getSetCC(DL, SetCCType, NewX, NewX, IsNum ? ISD::SETO : ISD::SETUO);
29024+
2899929025
return DAG.getSelect(DL, VT, IsNaN, NewX, MinMax);
2900029026
}
2900129027

@@ -33253,6 +33279,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3325333279
case ISD::UMIN: return LowerMINMAX(Op, Subtarget, DAG);
3325433280
case ISD::FMINIMUM:
3325533281
case ISD::FMAXIMUM:
33282+
case ISD::FMINIMUMNUM:
33283+
case ISD::FMAXIMUMNUM:
3325633284
return LowerFMINIMUM_FMAXIMUM(Op, Subtarget, DAG);
3325733285
case ISD::ABS: return LowerABS(Op, Subtarget, DAG);
3325833286
case ISD::ABDS:
@@ -45994,6 +46022,8 @@ static SDValue scalarizeExtEltFP(SDNode *ExtElt, SelectionDAG &DAG,
4599446022
case ISD::FMAXNUM_IEEE:
4599546023
case ISD::FMAXIMUM:
4599646024
case ISD::FMINIMUM:
46025+
case ISD::FMAXIMUMNUM:
46026+
case ISD::FMINIMUMNUM:
4599746027
case X86ISD::FMAX:
4599846028
case X86ISD::FMIN:
4599946029
case ISD::FABS: // Begin 1 operand

‎llvm/test/CodeGen/AMDGPU/maximumnum.ll

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1838,11 +1838,11 @@ define <3 x half> @v_maximumnum_v3f16(<3 x half> %x, <3 x half> %y) {
18381838
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
18391839
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
18401840
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1841-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1842-
; GFX8-NEXT: v_max_f16_e32 v2, v3, v3
1841+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
18431842
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
1843+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1844+
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
18441845
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
1845-
; GFX8-NEXT: v_max_f16_e32 v1, v1, v2
18461846
; GFX8-NEXT: s_setpc_b64 s[30:31]
18471847
;
18481848
; GFX9-LABEL: v_maximumnum_v3f16:
@@ -1904,8 +1904,8 @@ define <3 x half> @v_maximumnum_v3f16_nnan(<3 x half> %x, <3 x half> %y) {
19041904
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19051905
; GFX8-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
19061906
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1907-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
19081907
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
1908+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
19091909
; GFX8-NEXT: s_setpc_b64 s[30:31]
19101910
;
19111911
; GFX9-LABEL: v_maximumnum_v3f16_nnan:
@@ -1947,20 +1947,20 @@ define <4 x half> @v_maximumnum_v4f16(<4 x half> %x, <4 x half> %y) {
19471947
; GFX8-LABEL: v_maximumnum_v4f16:
19481948
; GFX8: ; %bb.0:
19491949
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1950-
; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1951-
; GFX8-NEXT: v_max_f16_sdwa v5, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1952-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
1953-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
1950+
; GFX8-NEXT: v_max_f16_sdwa v4, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1951+
; GFX8-NEXT: v_max_f16_sdwa v5, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
19541952
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1955-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1956-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
1957-
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1958-
; GFX8-NEXT: v_max_f16_sdwa v4, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1953+
; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1954+
; GFX8-NEXT: v_max_f16_sdwa v6, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
19591955
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
19601956
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
1961-
; GFX8-NEXT: v_max_f16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1957+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
1958+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
1959+
; GFX8-NEXT: v_max_f16_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
19621960
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
1963-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
1961+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1962+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
1963+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
19641964
; GFX8-NEXT: s_setpc_b64 s[30:31]
19651965
;
19661966
; GFX9-LABEL: v_maximumnum_v4f16:
@@ -2020,12 +2020,12 @@ define <4 x half> @v_maximumnum_v4f16_nnan(<4 x half> %x, <4 x half> %y) {
20202020
; GFX8-LABEL: v_maximumnum_v4f16_nnan:
20212021
; GFX8: ; %bb.0:
20222022
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2023-
; GFX8-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2024-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
2025-
; GFX8-NEXT: v_max_f16_sdwa v2, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2023+
; GFX8-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2024+
; GFX8-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
20262025
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
2027-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
2028-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
2026+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
2027+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
2028+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
20292029
; GFX8-NEXT: s_setpc_b64 s[30:31]
20302030
;
20312031
; GFX9-LABEL: v_maximumnum_v4f16_nnan:
@@ -2067,27 +2067,27 @@ define <6 x half> @v_maximumnum_v6f16(<6 x half> %x, <6 x half> %y) {
20672067
; GFX8-LABEL: v_maximumnum_v6f16:
20682068
; GFX8: ; %bb.0:
20692069
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2070-
; GFX8-NEXT: v_max_f16_sdwa v6, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2071-
; GFX8-NEXT: v_max_f16_sdwa v7, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2072-
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2073-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2070+
; GFX8-NEXT: v_max_f16_sdwa v6, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2071+
; GFX8-NEXT: v_max_f16_sdwa v7, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
20742072
; GFX8-NEXT: v_max_f16_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2075-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v3
2076-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
2077-
; GFX8-NEXT: v_max_f16_sdwa v3, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2078-
; GFX8-NEXT: v_max_f16_sdwa v6, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2073+
; GFX8-NEXT: v_max_f16_sdwa v7, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2074+
; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2075+
; GFX8-NEXT: v_max_f16_sdwa v7, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2076+
; GFX8-NEXT: v_max_f16_sdwa v8, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2077+
; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2078+
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
2079+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
20792080
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
20802081
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
2081-
; GFX8-NEXT: v_max_f16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2082+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2083+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2084+
; GFX8-NEXT: v_max_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2085+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v5
20822086
; GFX8-NEXT: v_max_f16_e32 v1, v1, v4
2083-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
2084-
; GFX8-NEXT: v_max_f16_sdwa v3, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2085-
; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2086-
; GFX8-NEXT: v_max_f16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2087-
; GFX8-NEXT: v_max_f16_e32 v4, v5, v5
2088-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
2089-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v4
2090-
; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
2087+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v3
2088+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v8
2089+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v7
2090+
; GFX8-NEXT: v_or_b32_e32 v2, v2, v6
20912091
; GFX8-NEXT: s_setpc_b64 s[30:31]
20922092
;
20932093
; GFX9-LABEL: v_maximumnum_v6f16:
@@ -2159,34 +2159,34 @@ define <8 x half> @v_maximumnum_v8f16(<8 x half> %x, <8 x half> %y) {
21592159
; GFX8-LABEL: v_maximumnum_v8f16:
21602160
; GFX8: ; %bb.0:
21612161
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2162-
; GFX8-NEXT: v_max_f16_sdwa v8, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2163-
; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2164-
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
2165-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2162+
; GFX8-NEXT: v_max_f16_sdwa v8, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2163+
; GFX8-NEXT: v_max_f16_sdwa v9, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
21662164
; GFX8-NEXT: v_max_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2167-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v4
2168-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v8
2169-
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2170-
; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2165+
; GFX8-NEXT: v_max_f16_sdwa v9, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2166+
; GFX8-NEXT: v_max_f16_sdwa v10, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2167+
; GFX8-NEXT: v_max_f16_sdwa v9, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2168+
; GFX8-NEXT: v_max_f16_sdwa v10, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2169+
; GFX8-NEXT: v_max_f16_sdwa v11, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2170+
; GFX8-NEXT: v_max_f16_sdwa v10, v11, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2171+
; GFX8-NEXT: v_max_f16_sdwa v11, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2172+
; GFX8-NEXT: v_max_f16_sdwa v12, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2173+
; GFX8-NEXT: v_max_f16_e32 v7, v7, v7
2174+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2175+
; GFX8-NEXT: v_max_f16_e32 v6, v6, v6
2176+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
21712177
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
21722178
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
2173-
; GFX8-NEXT: v_max_f16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2179+
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
2180+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2181+
; GFX8-NEXT: v_max_f16_sdwa v11, v12, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2182+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v7
2183+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
21742184
; GFX8-NEXT: v_max_f16_e32 v1, v1, v5
2175-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
2176-
; GFX8-NEXT: v_max_f16_sdwa v4, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2177-
; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2178-
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2179-
; GFX8-NEXT: v_max_f16_e32 v5, v6, v6
2180-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
2181-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v5
2182-
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
2183-
; GFX8-NEXT: v_max_f16_sdwa v4, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2184-
; GFX8-NEXT: v_max_f16_sdwa v5, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2185-
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2186-
; GFX8-NEXT: v_max_f16_e32 v5, v7, v7
2187-
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2188-
; GFX8-NEXT: v_max_f16_e32 v3, v3, v5
2189-
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
2185+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v4
2186+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v11
2187+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v10
2188+
; GFX8-NEXT: v_or_b32_e32 v2, v2, v9
2189+
; GFX8-NEXT: v_or_b32_e32 v3, v3, v8
21902190
; GFX8-NEXT: s_setpc_b64 s[30:31]
21912191
;
21922192
; GFX9-LABEL: v_maximumnum_v8f16:

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