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[AArch64] Basic SVE PCS support for handling scalable vectors on Darwin.
For the tests I just added +sve instead of what actual hardware has, which is only SME, since otherwise all the test functions need to be marked as streaming mode. rdar://121864771
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‎llvm/lib/Target/AArch64/AArch64CallingConvention.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -376,6 +376,18 @@ def CC_AArch64_DarwinPCS : CallingConv<[
376376

377377
CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
378378

379+
CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,
380+
nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],
381+
CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
382+
CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,
383+
nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],
384+
CCPassIndirect<i64>>,
385+
386+
CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount],
387+
CCAssignToReg<[P0, P1, P2, P3]>>,
388+
CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount],
389+
CCPassIndirect<i64>>,
390+
379391
// Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
380392
// up to eight each of GPR and FPR.
381393
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
@@ -602,6 +614,11 @@ def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23),
602614
X19, X20, X21, X22, X23, X24,
603615
X25, X26, X27, X28, LR, FP)>;
604616

617+
def CSR_Darwin_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23),
618+
(sequence "P%u", 4, 15),
619+
LR, FP, X19, X20, X21, X22,
620+
X23, X24, X25, X26, X27, X28)>;
621+
605622
// SME ABI support routines such as __arm_tpidr2_save/restore preserve most registers.
606623
def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0
607624
: CalleeSavedRegs<(add (sequence "Z%u", 0, 31),

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2857,11 +2857,12 @@ static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
28572857
static bool produceCompactUnwindFrame(MachineFunction &MF) {
28582858
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
28592859
AttributeList Attrs = MF.getFunction().getAttributes();
2860+
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
28602861
return Subtarget.isTargetMachO() &&
28612862
!(Subtarget.getTargetLowering()->supportSwiftError() &&
28622863
Attrs.hasAttrSomewhere(Attribute::SwiftError)) &&
28632864
MF.getFunction().getCallingConv() != CallingConv::SwiftTail &&
2864-
!requiresSaveVG(MF);
2865+
!requiresSaveVG(MF) && AFI->getSVECalleeSavedStackSize() == 0;
28652866
}
28662867

28672868
static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,8 @@ AArch64RegisterInfo::getDarwinCalleeSavedRegs(const MachineFunction *MF) const {
197197
return CSR_Darwin_AArch64_RT_AllRegs_SaveList;
198198
if (MF->getFunction().getCallingConv() == CallingConv::Win64)
199199
return CSR_Darwin_AArch64_AAPCS_Win64_SaveList;
200+
if (MF->getInfo<AArch64FunctionInfo>()->isSVECC())
201+
return CSR_Darwin_AArch64_SVE_AAPCS_SaveList;
200202
return CSR_Darwin_AArch64_AAPCS_SaveList;
201203
}
202204

@@ -250,8 +252,7 @@ AArch64RegisterInfo::getDarwinCallPreservedMask(const MachineFunction &MF,
250252
if (CC == CallingConv::AArch64_VectorCall)
251253
return CSR_Darwin_AArch64_AAVPCS_RegMask;
252254
if (CC == CallingConv::AArch64_SVE_VectorCall)
253-
report_fatal_error(
254-
"Calling convention SVE_VectorCall is unsupported on Darwin.");
255+
return CSR_Darwin_AArch64_SVE_AAPCS_RegMask;
255256
if (CC == CallingConv::AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0)
256257
return CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0_RegMask;
257258
if (CC == CallingConv::AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1)

‎llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
1-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s
1+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s --check-prefixes=CHECK,LINUX
2+
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s --check-prefixes=CHECK,DARWIN
23

34
; Test that z8 and z9, passed in by reference, are correctly loaded from x0 and x1.
45
; i.e. z0 = %z0
@@ -97,7 +98,8 @@ define aarch64_sve_vector_pcs <vscale x 16 x i1> @caller_with_svepred_arg_1xv16i
9798
; CHECK: STR_PXI [[PRED0]], %stack.0, 0 :: (store (<vscale x 1 x s16>) into %stack.0)
9899
; CHECK: [[STACK:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
99100
; CHECK: $x0 = COPY [[STACK]]
100-
; CHECK: BL @callee_with_svepred_arg_4xv16i1_1xv16i1, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $p1, implicit $p2, implicit $p3, implicit $x0, implicit-def $sp, implicit-def $p0
101+
; LINUX: BL @callee_with_svepred_arg_4xv16i1_1xv16i1, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $p1, implicit $p2, implicit $p3, implicit $x0, implicit-def $sp, implicit-def $p0
102+
; DARWIN: BL @callee_with_svepred_arg_4xv16i1_1xv16i1, csr_darwin_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $p1, implicit $p2, implicit $p3, implicit $x0, implicit-def $sp, implicit-def $p0
101103
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
102104
%res = call <vscale x 16 x i1> @callee_with_svepred_arg_4xv16i1_1xv16i1([4 x <vscale x 16 x i1>] %arg2, [1 x <vscale x 16 x i1>] %arg1)
103105
ret <vscale x 16 x i1> %res
@@ -157,7 +159,8 @@ define [4 x <vscale x 16 x i1>] @caller_with_svepred_arg_4xv16i1_4xv16i1([4 x <v
157159
; CHECK: STR_PXI [[PRED1]], killed [[ADDR1]], 0 :: (store (<vscale x 1 x s16>))
158160
; CHECK: STR_PXI [[PRED0]], %stack.0, 0 :: (store (<vscale x 1 x s16>) into %stack.0)
159161
; CHECK: $x0 = COPY [[STACK]]
160-
; CHECK: BL @callee_with_svepred_arg_4xv16i1_4xv16i1, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $p1, implicit $p2, implicit $p3, implicit $x0, implicit-def $sp, implicit-def $p0, implicit-def $p1, implicit-def $p2, implicit-def $p3
162+
; LINUX: BL @callee_with_svepred_arg_4xv16i1_4xv16i1, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $p1, implicit $p2, implicit $p3, implicit $x0, implicit-def $sp, implicit-def $p0, implicit-def $p1, implicit-def $p2, implicit-def $p3
163+
; DARWIN: BL @callee_with_svepred_arg_4xv16i1_4xv16i1, csr_darwin_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $p1, implicit $p2, implicit $p3, implicit $x0, implicit-def $sp, implicit-def $p0, implicit-def $p1, implicit-def $p2, implicit-def $p3
161164
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
162165
%res = call [4 x <vscale x 16 x i1>] @callee_with_svepred_arg_4xv16i1_4xv16i1([4 x <vscale x 16 x i1>] %arg2, [4 x <vscale x 16 x i1>] %arg1)
163166
ret [4 x <vscale x 16 x i1>] %res
@@ -217,7 +220,8 @@ define [2 x <vscale x 32 x i1>] @caller_with_svepred_arg_2xv32i1_1xv16i1([2 x <v
217220
; CHECK: STR_PXI [[PRED1]], killed [[ADDR1]], 0 :: (store (<vscale x 1 x s16>))
218221
; CHECK: STR_PXI [[PRED0]], %stack.0, 0 :: (store (<vscale x 1 x s16>) into %stack.0)
219222
; CHECK: $x0 = COPY [[STACK]]
220-
; CHECK: BL @callee_with_svepred_arg_1xv16i1_2xv32i1, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $x0, implicit-def $sp, implicit-def $p0, implicit-def $p1, implicit-def $p2, implicit-def $p3
223+
; LINUX: BL @callee_with_svepred_arg_1xv16i1_2xv32i1, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $x0, implicit-def $sp, implicit-def $p0, implicit-def $p1, implicit-def $p2, implicit-def $p3
224+
; DARWIN: BL @callee_with_svepred_arg_1xv16i1_2xv32i1, csr_darwin_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $p0, implicit $x0, implicit-def $sp, implicit-def $p0, implicit-def $p1, implicit-def $p2, implicit-def $p3
221225
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
222226
%res = call [2 x <vscale x 32 x i1>] @callee_with_svepred_arg_1xv16i1_2xv32i1([1 x <vscale x 16 x i1>] %arg2, [2 x <vscale x 32 x i1>] %arg1)
223227
ret [2 x <vscale x 32 x i1>] %res

‎llvm/test/CodeGen/AArch64/sve-calling-convention.ll

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,96 +1,123 @@
11
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=DARWIN
23
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=prologepilog < %s | FileCheck %s --check-prefix=CHECKCSR
4+
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=prologepilog < %s | FileCheck %s --check-prefix=CHECKCSR
35

46
; CHECK-LABEL: name: nosve_signature
7+
; DARWIN-LABEL: name: nosve_signature
58
define i32 @nosve_signature() nounwind {
69
ret i32 42
710
}
811

912
; CHECK-LABEL: name: sve_signature_ret_vec
13+
; DARWIN-LABEL: name: sve_signature_ret_vec
1014
define <vscale x 4 x i32> @sve_signature_ret_vec() nounwind {
1115
ret <vscale x 4 x i32> undef
1216
}
1317

1418
; CHECK-LABEL: name: sve_signature_ret_pred
19+
; DARWIN-LABEL: name: sve_signature_ret_pred
1520
define <vscale x 4 x i1> @sve_signature_ret_pred() nounwind {
1621
ret <vscale x 4 x i1> undef
1722
}
1823

1924
; CHECK-LABEL: name: sve_signature_arg_vec
25+
; DARWIN-LABEL: name: sve_signature_arg_vec
2026
define void @sve_signature_arg_vec(<vscale x 4 x i32> %arg) nounwind {
2127
ret void
2228
}
2329

2430
; CHECK-LABEL: name: sve_signature_arg_pred
31+
; DARWIN-LABEL: name: sve_signature_arg_pred
2532
define void @sve_signature_arg_pred(<vscale x 4 x i1> %arg) nounwind {
2633
ret void
2734
}
2835

2936
; CHECK-LABEL: name: caller_nosve_signature
3037
; CHECK: BL @nosve_signature, csr_aarch64_aapcs
38+
; DARWIN-LABEL: name: caller_nosve_signature
39+
; DARWIN: BL @nosve_signature, csr_darwin_aarch64_aapcs
3140
define i32 @caller_nosve_signature() nounwind {
3241
%res = call i32 @nosve_signature()
3342
ret i32 %res
3443
}
3544

3645
; CHECK-LABEL: name: caller_nosve_signature_fastcc
3746
; CHECK: BL @nosve_signature, csr_aarch64_aapcs
47+
; DARWIN-LABEL: name: caller_nosve_signature_fastcc
48+
; DARWIN: BL @nosve_signature, csr_darwin_aarch64_aapcs
3849
define i32 @caller_nosve_signature_fastcc() nounwind {
3950
%res = call fastcc i32 @nosve_signature()
4051
ret i32 %res
4152
}
4253

4354
; CHECK-LABEL: name: sve_signature_ret_vec_caller
4455
; CHECK: BL @sve_signature_ret_vec, csr_aarch64_sve_aapcs
56+
; DARWIN-LABEL: name: sve_signature_ret_vec_caller
57+
; DARWIN: BL @sve_signature_ret_vec, csr_darwin_aarch64_sve_aapcs
4558
define <vscale x 4 x i32> @sve_signature_ret_vec_caller() nounwind {
4659
%res = call <vscale x 4 x i32> @sve_signature_ret_vec()
4760
ret <vscale x 4 x i32> %res
4861
}
4962

5063
; CHECK-LABEL: name: sve_signature_ret_vec_caller_fastcc
5164
; CHECK: BL @sve_signature_ret_vec, csr_aarch64_sve_aapcs
65+
; DARWIN-LABEL: name: sve_signature_ret_vec_caller_fastcc
66+
; DARWIN: BL @sve_signature_ret_vec, csr_darwin_aarch64_sve_aapcs
5267
define <vscale x 4 x i32> @sve_signature_ret_vec_caller_fastcc() nounwind {
5368
%res = call fastcc <vscale x 4 x i32> @sve_signature_ret_vec()
5469
ret <vscale x 4 x i32> %res
5570
}
5671

5772
; CHECK-LABEL: name: sve_signature_ret_pred_caller
5873
; CHECK: BL @sve_signature_ret_pred, csr_aarch64_sve_aapcs
74+
; DARWIN-LABEL: name: sve_signature_ret_pred_caller
75+
; DARWIN: BL @sve_signature_ret_pred, csr_darwin_aarch64_sve_aapcs
5976
define <vscale x 4 x i1> @sve_signature_ret_pred_caller() nounwind {
6077
%res = call <vscale x 4 x i1> @sve_signature_ret_pred()
6178
ret <vscale x 4 x i1> %res
6279
}
6380

6481
; CHECK-LABEL: name: sve_signature_ret_pred_caller_fastcc
6582
; CHECK: BL @sve_signature_ret_pred, csr_aarch64_sve_aapcs
83+
; DARWIN-LABEL: name: sve_signature_ret_pred_caller_fastcc
84+
; DARWIN: BL @sve_signature_ret_pred, csr_darwin_aarch64_sve_aapcs
6685
define <vscale x 4 x i1> @sve_signature_ret_pred_caller_fastcc() nounwind {
6786
%res = call fastcc <vscale x 4 x i1> @sve_signature_ret_pred()
6887
ret <vscale x 4 x i1> %res
6988
}
7089

7190
; CHECK-LABEL: name: sve_signature_arg_vec_caller
7291
; CHECK: BL @sve_signature_arg_vec, csr_aarch64_sve_aapcs
92+
; DARWIN-LABEL: name: sve_signature_arg_vec_caller
93+
; DARWIN: BL @sve_signature_arg_vec, csr_darwin_aarch64_sve_aapcs
7394
define void @sve_signature_arg_vec_caller(<vscale x 4 x i32> %arg) nounwind {
7495
call void @sve_signature_arg_vec(<vscale x 4 x i32> %arg)
7596
ret void
7697
}
7798

7899
; CHECK-LABEL: name: sve_signature_arg_vec_caller_fastcc
79100
; CHECK: BL @sve_signature_arg_vec, csr_aarch64_sve_aapcs
101+
; DARWIN-LABEL: name: sve_signature_arg_vec_caller_fastcc
102+
; DARWIN: BL @sve_signature_arg_vec, csr_darwin_aarch64_sve_aapcs
80103
define void @sve_signature_arg_vec_caller_fastcc(<vscale x 4 x i32> %arg) nounwind {
81104
call fastcc void @sve_signature_arg_vec(<vscale x 4 x i32> %arg)
82105
ret void
83106
}
84107

85108
; CHECK-LABEL: name: sve_signature_arg_pred_caller
86109
; CHECK: BL @sve_signature_arg_pred, csr_aarch64_sve_aapcs
110+
; DARWIN-LABEL: name: sve_signature_arg_pred_caller
111+
; DARWIN: BL @sve_signature_arg_pred, csr_darwin_aarch64_sve_aapcs
87112
define void @sve_signature_arg_pred_caller(<vscale x 4 x i1> %arg) nounwind {
88113
call void @sve_signature_arg_pred(<vscale x 4 x i1> %arg)
89114
ret void
90115
}
91116

92117
; CHECK-LABEL: name: sve_signature_arg_pred_caller_fastcc
93118
; CHECK: BL @sve_signature_arg_pred, csr_aarch64_sve_aapcs
119+
; DARWIN-LABEL: name: sve_signature_arg_pred_caller_fastcc
120+
; DARWIN: BL @sve_signature_arg_pred, csr_darwin_aarch64_sve_aapcs
94121
define void @sve_signature_arg_pred_caller_fastcc(<vscale x 4 x i1> %arg) nounwind {
95122
call fastcc void @sve_signature_arg_pred(<vscale x 4 x i1> %arg)
96123
ret void
@@ -100,6 +127,10 @@ define void @sve_signature_arg_pred_caller_fastcc(<vscale x 4 x i1> %arg) nounwi
100127
; CHECK: [[RES:%[0-9]+]]:zpr = COPY $z7
101128
; CHECK: $z0 = COPY [[RES]]
102129
; CHECK: RET_ReallyLR implicit $z0
130+
; DARWIN-LABEL: name: sve_signature_many_arg_vec
131+
; DARWIN: [[RES:%[0-9]+]]:zpr = COPY $z7
132+
; DARWIN: $z0 = COPY [[RES]]
133+
; DARWIN: RET_ReallyLR implicit $z0
103134
define <vscale x 4 x i32> @sve_signature_many_arg_vec(<vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2, <vscale x 4 x i32> %arg3, <vscale x 4 x i32> %arg4, <vscale x 4 x i32> %arg5, <vscale x 4 x i32> %arg6, <vscale x 4 x i32> %arg7, <vscale x 4 x i32> %arg8) nounwind {
104135
ret <vscale x 4 x i32> %arg8
105136
}
@@ -108,6 +139,10 @@ define <vscale x 4 x i32> @sve_signature_many_arg_vec(<vscale x 4 x i32> %arg1,
108139
; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p3
109140
; CHECK: $p0 = COPY [[RES]]
110141
; CHECK: RET_ReallyLR implicit $p0
142+
; DARWIN-LABEL: name: sve_signature_many_arg_pred
143+
; DARWIN: [[RES:%[0-9]+]]:ppr = COPY $p3
144+
; DARWIN: $p0 = COPY [[RES]]
145+
; DARWIN: RET_ReallyLR implicit $p0
111146
define <vscale x 4 x i1> @sve_signature_many_arg_pred(<vscale x 4 x i1> %arg1, <vscale x 4 x i1> %arg2, <vscale x 4 x i1> %arg3, <vscale x 4 x i1> %arg4) nounwind {
112147
ret <vscale x 4 x i1> %arg4
113148
}
@@ -116,6 +151,10 @@ define <vscale x 4 x i1> @sve_signature_many_arg_pred(<vscale x 4 x i1> %arg1, <
116151
; CHECK: [[RES:%[0-9]+]]:zpr = COPY $z1
117152
; CHECK: $z0 = COPY [[RES]]
118153
; CHECK: RET_ReallyLR implicit $z0
154+
; DARWIN-LABEL: name: sve_signature_vec
155+
; DARWIN: [[RES:%[0-9]+]]:zpr = COPY $z1
156+
; DARWIN: $z0 = COPY [[RES]]
157+
; DARWIN: RET_ReallyLR implicit $z0
119158
define <vscale x 4 x i32> @sve_signature_vec(<vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2) nounwind {
120159
ret <vscale x 4 x i32> %arg2
121160
}
@@ -124,6 +163,10 @@ define <vscale x 4 x i32> @sve_signature_vec(<vscale x 4 x i32> %arg1, <vscale x
124163
; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p1
125164
; CHECK: $p0 = COPY [[RES]]
126165
; CHECK: RET_ReallyLR implicit $p0
166+
; DARWIN-LABEL: name: sve_signature_pred
167+
; DARWIN: [[RES:%[0-9]+]]:ppr = COPY $p1
168+
; DARWIN: $p0 = COPY [[RES]]
169+
; DARWIN: RET_ReallyLR implicit $p0
127170
define <vscale x 4 x i1> @sve_signature_pred(<vscale x 4 x i1> %arg1, <vscale x 4 x i1> %arg2) nounwind {
128171
ret <vscale x 4 x i1> %arg2
129172
}
@@ -183,6 +226,15 @@ define [2 x <vscale x 32 x i1>] @sve_signature_pred_2xv32i1([2 x <vscale x 32 x
183226
; CHECK: [[RES:%[0-9]+]]:zpr = COPY $z0
184227
; CHECK: $z0 = COPY [[RES]]
185228
; CHECK: RET_ReallyLR implicit $z0
229+
; DARWIN-LABEL: name: sve_signature_vec_caller
230+
; DARWIN-DAG: [[ARG2:%[0-9]+]]:zpr = COPY $z1
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; DARWIN-DAG: [[ARG1:%[0-9]+]]:zpr = COPY $z0
232+
; DARWIN-DAG: $z0 = COPY [[ARG2]]
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; DARWIN-DAG: $z1 = COPY [[ARG1]]
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; DARWIN-NEXT: BL @sve_signature_vec, csr_darwin_aarch64_sve_aapcs
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; DARWIN: [[RES:%[0-9]+]]:zpr = COPY $z0
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; DARWIN: $z0 = COPY [[RES]]
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; DARWIN: RET_ReallyLR implicit $z0
186238
define <vscale x 4 x i32> @sve_signature_vec_caller(<vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2) nounwind {
187239
%res = call <vscale x 4 x i32> @sve_signature_vec(<vscale x 4 x i32> %arg2, <vscale x 4 x i32> %arg1)
188240
ret <vscale x 4 x i32> %res
@@ -197,6 +249,15 @@ define <vscale x 4 x i32> @sve_signature_vec_caller(<vscale x 4 x i32> %arg1, <v
197249
; CHECK: [[RES:%[0-9]+]]:ppr = COPY $p0
198250
; CHECK: $p0 = COPY [[RES]]
199251
; CHECK: RET_ReallyLR implicit $p0
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; DARWIN-LABEL: name: sve_signature_pred_caller
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; DARWIN-DAG: [[ARG2:%[0-9]+]]:ppr = COPY $p1
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; DARWIN-DAG: [[ARG1:%[0-9]+]]:ppr = COPY $p0
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; DARWIN-DAG: $p0 = COPY [[ARG2]]
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; DARWIN-DAG: $p1 = COPY [[ARG1]]
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; DARWIN-NEXT: BL @sve_signature_pred, csr_darwin_aarch64_sve_aapcs
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; DARWIN: [[RES:%[0-9]+]]:ppr = COPY $p0
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; DARWIN: $p0 = COPY [[RES]]
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; DARWIN: RET_ReallyLR implicit $p0
200261
define <vscale x 4 x i1> @sve_signature_pred_caller(<vscale x 4 x i1> %arg1, <vscale x 4 x i1> %arg2) nounwind {
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%res = call <vscale x 4 x i1> @sve_signature_pred(<vscale x 4 x i1> %arg2, <vscale x 4 x i1> %arg1)
202263
ret <vscale x 4 x i1> %res

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