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[RISCV] Move VFMADD_VL DAG combine to a function. NFC
This is preparation for an additional combine.
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+39
-36
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1 file changed

+39
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 39 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -11201,6 +11201,43 @@ static unsigned negateFMAOpcode(unsigned Opcode, bool NegMul, bool NegAcc) {
1120111201
return Opcode;
1120211202
}
1120311203

11204+
static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG) {
11205+
// Fold FNEG_VL into FMA opcodes.
11206+
// The first operand of strict-fp is chain.
11207+
unsigned Offset = N->isTargetStrictFPOpcode();
11208+
SDValue A = N->getOperand(0 + Offset);
11209+
SDValue B = N->getOperand(1 + Offset);
11210+
SDValue C = N->getOperand(2 + Offset);
11211+
SDValue Mask = N->getOperand(3 + Offset);
11212+
SDValue VL = N->getOperand(4 + Offset);
11213+
11214+
auto invertIfNegative = [&Mask, &VL](SDValue &V) {
11215+
if (V.getOpcode() == RISCVISD::FNEG_VL && V.getOperand(1) == Mask &&
11216+
V.getOperand(2) == VL) {
11217+
// Return the negated input.
11218+
V = V.getOperand(0);
11219+
return true;
11220+
}
11221+
11222+
return false;
11223+
};
11224+
11225+
bool NegA = invertIfNegative(A);
11226+
bool NegB = invertIfNegative(B);
11227+
bool NegC = invertIfNegative(C);
11228+
11229+
// If no operands are negated, we're done.
11230+
if (!NegA && !NegB && !NegC)
11231+
return SDValue();
11232+
11233+
unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC);
11234+
if (N->isTargetStrictFPOpcode())
11235+
return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(),
11236+
{N->getOperand(0), A, B, C, Mask, VL});
11237+
return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
11238+
VL);
11239+
}
11240+
1120411241
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
1120511242
const RISCVSubtarget &Subtarget) {
1120611243
assert(N->getOpcode() == ISD::SRA && "Unexpected opcode");
@@ -12073,42 +12110,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1207312110
case RISCVISD::STRICT_VFMADD_VL:
1207412111
case RISCVISD::STRICT_VFNMADD_VL:
1207512112
case RISCVISD::STRICT_VFMSUB_VL:
12076-
case RISCVISD::STRICT_VFNMSUB_VL: {
12077-
// Fold FNEG_VL into FMA opcodes.
12078-
// The first operand of strict-fp is chain.
12079-
unsigned Offset = N->isTargetStrictFPOpcode();
12080-
SDValue A = N->getOperand(0 + Offset);
12081-
SDValue B = N->getOperand(1 + Offset);
12082-
SDValue C = N->getOperand(2 + Offset);
12083-
SDValue Mask = N->getOperand(3 + Offset);
12084-
SDValue VL = N->getOperand(4 + Offset);
12085-
12086-
auto invertIfNegative = [&Mask, &VL](SDValue &V) {
12087-
if (V.getOpcode() == RISCVISD::FNEG_VL && V.getOperand(1) == Mask &&
12088-
V.getOperand(2) == VL) {
12089-
// Return the negated input.
12090-
V = V.getOperand(0);
12091-
return true;
12092-
}
12093-
12094-
return false;
12095-
};
12096-
12097-
bool NegA = invertIfNegative(A);
12098-
bool NegB = invertIfNegative(B);
12099-
bool NegC = invertIfNegative(C);
12100-
12101-
// If no operands are negated, we're done.
12102-
if (!NegA && !NegB && !NegC)
12103-
return SDValue();
12104-
12105-
unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC);
12106-
if (Offset > 0)
12107-
return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(),
12108-
{N->getOperand(0), A, B, C, Mask, VL});
12109-
return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
12110-
VL);
12111-
}
12113+
case RISCVISD::STRICT_VFNMSUB_VL:
12114+
return performVFMADD_VLCombine(N, DAG);
1211212115
case ISD::LOAD:
1211312116
case ISD::STORE: {
1211412117
if (DCI.isAfterLegalizeDAG())

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