@@ -11201,6 +11201,43 @@ static unsigned negateFMAOpcode(unsigned Opcode, bool NegMul, bool NegAcc) {
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return Opcode;
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}
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+ static SDValue performVFMADD_VLCombine(SDNode *N, SelectionDAG &DAG) {
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+ // Fold FNEG_VL into FMA opcodes.
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+ // The first operand of strict-fp is chain.
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+ unsigned Offset = N->isTargetStrictFPOpcode();
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+ SDValue A = N->getOperand(0 + Offset);
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+ SDValue B = N->getOperand(1 + Offset);
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+ SDValue C = N->getOperand(2 + Offset);
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+ SDValue Mask = N->getOperand(3 + Offset);
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+ SDValue VL = N->getOperand(4 + Offset);
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+
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+ auto invertIfNegative = [&Mask, &VL](SDValue &V) {
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+ if (V.getOpcode() == RISCVISD::FNEG_VL && V.getOperand(1) == Mask &&
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+ V.getOperand(2) == VL) {
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+ // Return the negated input.
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+ V = V.getOperand(0);
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+ return true;
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+ }
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+
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+ return false;
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+ };
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+
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+ bool NegA = invertIfNegative(A);
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+ bool NegB = invertIfNegative(B);
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+ bool NegC = invertIfNegative(C);
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+
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+ // If no operands are negated, we're done.
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+ if (!NegA && !NegB && !NegC)
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+ return SDValue();
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+
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+ unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC);
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+ if (N->isTargetStrictFPOpcode())
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+ return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(),
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+ {N->getOperand(0), A, B, C, Mask, VL});
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+ return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
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+ VL);
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+ }
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+
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static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
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const RISCVSubtarget &Subtarget) {
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assert(N->getOpcode() == ISD::SRA && "Unexpected opcode");
@@ -12073,42 +12110,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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case RISCVISD::STRICT_VFMADD_VL:
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case RISCVISD::STRICT_VFNMADD_VL:
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case RISCVISD::STRICT_VFMSUB_VL:
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- case RISCVISD::STRICT_VFNMSUB_VL: {
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- // Fold FNEG_VL into FMA opcodes.
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- // The first operand of strict-fp is chain.
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- unsigned Offset = N->isTargetStrictFPOpcode();
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- SDValue A = N->getOperand(0 + Offset);
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- SDValue B = N->getOperand(1 + Offset);
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- SDValue C = N->getOperand(2 + Offset);
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- SDValue Mask = N->getOperand(3 + Offset);
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- SDValue VL = N->getOperand(4 + Offset);
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-
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- auto invertIfNegative = [&Mask, &VL](SDValue &V) {
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- if (V.getOpcode() == RISCVISD::FNEG_VL && V.getOperand(1) == Mask &&
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- V.getOperand(2) == VL) {
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- // Return the negated input.
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- V = V.getOperand(0);
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- return true;
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- }
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-
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- return false;
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- };
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-
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- bool NegA = invertIfNegative(A);
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- bool NegB = invertIfNegative(B);
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- bool NegC = invertIfNegative(C);
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-
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- // If no operands are negated, we're done.
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- if (!NegA && !NegB && !NegC)
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- return SDValue();
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-
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- unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC);
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- if (Offset > 0)
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- return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(),
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- {N->getOperand(0), A, B, C, Mask, VL});
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- return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
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- VL);
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- }
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+ case RISCVISD::STRICT_VFNMSUB_VL:
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+ return performVFMADD_VLCombine(N, DAG);
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case ISD::LOAD:
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case ISD::STORE: {
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if (DCI.isAfterLegalizeDAG())
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