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1 parent b8c097e commit 3a5c127Copy full SHA for 3a5c127
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -3743,7 +3743,7 @@ InstructionCost AArch64TTIImpl::getInterleavedMemoryOpCost(
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assert(Factor >= 2 && "Invalid interleave factor");
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auto *VecVTy = cast<VectorType>(VecTy);
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- if (VecTy->isScalableTy() && (!ST->hasSVE() || Factor != 2))
+ if (VecTy->isScalableTy() && !ST->hasSVE())
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return InstructionCost::getInvalid();
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// Vectorization for masked interleaved accesses is only enabled for scalable
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