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FP8 CVT/CVTL
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‎clang/include/clang/Basic/arm_sve.td

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@@ -2447,3 +2447,13 @@ let SVETargetGuard = "sve2,faminmax", SMETargetGuard = "sme2,faminmax" in {
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defm SVAMIN : SInstZPZZ<"svamin", "hfd", "aarch64_sve_famin", "aarch64_sve_famin_u">;
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defm SVAMAX : SInstZPZZ<"svamax", "hfd", "aarch64_sve_famax", "aarch64_sve_famax_u">;
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}
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let SVETargetGuard = "sve2,fp8", SMETargetGuard = "sme2,fp8" in {
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// 8-bit floating-point convert to BFloat16/Float16
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def SVF1CVT : SInst<"svcvt1_{d}[_mf8]_fpm", "d~>", "bh", MergeNone, "aarch64_sve_fp8_cvt1", [VerifyRuntimeMode, SetsFPMR]>;
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def SVF2CVT : SInst<"svcvt2_{d}[_mf8]_fpm", "d~>", "bh", MergeNone, "aarch64_sve_fp8_cvt2", [VerifyRuntimeMode, SetsFPMR]>;
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// 8-bit floating-point convert to BFloat16/Float16 (top)
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def SVF1CVTLT : SInst<"svcvtlt1_{d}[_mf8]_fpm", "d~>", "bh", MergeNone, "aarch64_sve_fp8_cvtlt1", [VerifyRuntimeMode, SetsFPMR]>;
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def SVF2CVTLT : SInst<"svcvtlt2_{d}[_mf8]_fpm", "d~>", "bh", MergeNone, "aarch64_sve_fp8_cvtlt2", [VerifyRuntimeMode, SetsFPMR]>;
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}

‎clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c

Lines changed: 173 additions & 0 deletions
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@@ -0,0 +1,173 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CHECK-CXX
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// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CHECK-CXX
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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// REQUIRES: aarch64-registered-target
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#ifdef __ARM_FEATURE_SME
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#include <arm_sme.h>
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#else
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#include <arm_sve.h>
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#endif
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#ifdef SVE_OVERLOADED_FORMS
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#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
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#else
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#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3
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#endif
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#ifdef __ARM_FEATURE_SME
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#define STREAMING __arm_streaming
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#else
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#define STREAMING
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#endif
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// CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvt1_bf16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z20test_svcvt1_bf16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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svbfloat16_t test_svcvt1_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvt1_bf16,_mf8,_fpm)(zn, fpm);
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}
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// CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z20test_svcvt2_bf16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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svbfloat16_t test_svcvt2_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvt2_bf16,_mf8,_fpm)(zn, fpm);
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}
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// CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvtlt1_bf16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z22test_svcvtlt1_bf16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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svbfloat16_t test_svcvtlt1_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvtlt1_bf16,_mf8,_fpm)(zn, fpm);
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}
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// CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvtlt2_bf16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z22test_svcvtlt2_bf16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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svbfloat16_t test_svcvtlt2_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvtlt2_bf16,_mf8,_fpm)(zn, fpm);
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}
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// CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvt1_f16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z19test_svcvt1_f16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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svfloat16_t test_svcvt1_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvt1_f16,_mf8,_fpm)(zn, fpm);
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}
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// CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvt2_f16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z19test_svcvt2_f16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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svfloat16_t test_svcvt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvt2_f16,_mf8,_fpm)(zn, fpm);
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}
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// CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvtlt1_f16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z21test_svcvtlt1_f16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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svfloat16_t test_svcvtlt1_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvtlt1_f16,_mf8,_fpm)(zn, fpm);
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}
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// CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvtlt2_f16_mf8(
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// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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// CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z21test_svcvtlt2_f16_mf8u13__SVMfloat8_tm(
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// CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
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// CHECK-CXX-NEXT: [[ENTRY:.*:]]
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// CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]])
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// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> [[ZN]])
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// CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]]
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//
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svfloat16_t test_svcvtlt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
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return SVE_ACLE_FUNC(svcvtlt2_f16,_mf8,_fpm)(zn, fpm);
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}

‎clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c

Lines changed: 24 additions & 0 deletions
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@@ -0,0 +1,24 @@
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -verify -emit-llvm %s
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#include <arm_sve.h>
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void test_features(svmfloat8_t zn, fpm_t fpm) {
8+
svcvt1_bf16_mf8_fpm(zn, fpm);
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// expected-error@-1 {{'svcvt1_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
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svcvt2_bf16_mf8_fpm(zn, fpm);
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// expected-error@-1 {{'svcvt2_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
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svcvtlt1_bf16_mf8_fpm(zn, fpm);
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// expected-error@-1 {{'svcvtlt1_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
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svcvtlt2_bf16_mf8_fpm(zn, fpm);
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// expected-error@-1 {{'svcvtlt2_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
16+
svcvt1_f16_mf8_fpm(zn, fpm);
17+
// expected-error@-1 {{'svcvt1_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
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svcvt2_f16_mf8_fpm(zn, fpm);
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// expected-error@-1 {{'svcvt2_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
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svcvtlt1_f16_mf8_fpm(zn, fpm);
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// expected-error@-1 {{'svcvtlt1_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
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svcvtlt2_f16_mf8_fpm(zn, fpm);
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// expected-error@-1 {{'svcvtlt2_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}}
24+
}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3864,3 +3864,20 @@ def int_aarch64_sve_famin_u : AdvSIMD_Pred2VectorArg_Intrinsic;
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// Neon absolute maximum and minimum
38653865
def int_aarch64_neon_famax : AdvSIMD_2VectorArg_Intrinsic;
38663866
def int_aarch64_neon_famin : AdvSIMD_2VectorArg_Intrinsic;
3867+
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//
3869+
// FP8 intrinsics
3870+
//
3871+
let TargetPrefix = "aarch64" in {
3872+
3873+
// Conversions
3874+
class SVE2_FP8_Cvt
3875+
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
3876+
[llvm_nxv16i8_ty],
3877+
[IntrReadMem, IntrInaccessibleMemOnly]>;
3878+
3879+
def int_aarch64_sve_fp8_cvt1 : SVE2_FP8_Cvt;
3880+
def int_aarch64_sve_fp8_cvt2 : SVE2_FP8_Cvt;
3881+
def int_aarch64_sve_fp8_cvtlt1 : SVE2_FP8_Cvt;
3882+
def int_aarch64_sve_fp8_cvtlt2 : SVE2_FP8_Cvt;
3883+
}

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4369,14 +4369,14 @@ let Predicates = [HasNonStreamingSVE2p2orSME2p2] in {
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//===----------------------------------------------------------------------===//
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let Predicates = [HasSVE2orSME2, HasFP8] in {
43714371
// FP8 upconvert
4372-
defm F1CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b00, "f1cvt">;
4373-
defm F2CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b01, "f2cvt">;
4374-
defm BF1CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b10, "bf1cvt">;
4375-
defm BF2CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b11, "bf2cvt">;
4376-
defm F1CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b00, "f1cvtlt">;
4377-
defm F2CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b01, "f2cvtlt">;
4378-
defm BF1CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b10, "bf1cvtlt">;
4379-
defm BF2CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b11, "bf2cvtlt">;
4372+
defm F1CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b00, "f1cvt", nxv8f16, int_aarch64_sve_fp8_cvt1>;
4373+
defm F2CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b01, "f2cvt", nxv8f16, int_aarch64_sve_fp8_cvt2>;
4374+
defm BF1CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b10, "bf1cvt", nxv8bf16, int_aarch64_sve_fp8_cvt1>;
4375+
defm BF2CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b11, "bf2cvt", nxv8bf16, int_aarch64_sve_fp8_cvt2>;
4376+
defm F1CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b00, "f1cvtlt", nxv8f16, int_aarch64_sve_fp8_cvtlt1>;
4377+
defm F2CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b01, "f2cvtlt", nxv8f16, int_aarch64_sve_fp8_cvtlt2>;
4378+
defm BF1CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b10, "bf1cvtlt", nxv8bf16, int_aarch64_sve_fp8_cvtlt1>;
4379+
defm BF2CVTLT_ZZ : sve2_fp8_cvt_single<0b1, 0b11, "bf2cvtlt", nxv8bf16, int_aarch64_sve_fp8_cvtlt2>;
43804380

43814381
// FP8 downconvert
43824382
defm FCVTN_Z2Z_HtoB : sve2_fp8_down_cvt_single<0b00, "fcvtn", ZZ_h_mul_r>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10733,10 +10733,15 @@ class sve2_fp8_cvt_single<bit L, bits<2> opc, string mnemonic,
1073310733
let Inst{9-5} = Zn;
1073410734
let Inst{4-0} = Zd;
1073510735
let Uses = [FPMR, FPCR];
10736+
10737+
let mayLoad = 1;
10738+
let mayStore = 0;
1073610739
}
1073710740

10738-
multiclass sve2_fp8_cvt_single<bit L, bits<2> opc, string mnemonic> {
10741+
multiclass sve2_fp8_cvt_single<bit L, bits<2> opc, string mnemonic, ValueType vtd, SDPatternOperator op> {
1073910742
def _BtoH : sve2_fp8_cvt_single<L, opc, mnemonic, ZPR16, ZPR8>;
10743+
10744+
def : SVE_1_Op_Pat<vtd, op, nxv16i8, !cast<Instruction>(NAME # _BtoH)>;
1074010745
}
1074110746

1074210747
// FP8 downconvert

‎llvm/test/CodeGen/AArch64/fp8-sve-cvt-cvtlt.ll

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mattr=+bf16,+sve2,+fp8 < %s | FileCheck %s
3+
; RUN: llc -mattr=+bf16,+sme2,+fp8 --force-streaming < %s | FileCheck %s
4+
5+
target triple = "aarch64-linux"
6+
7+
define <vscale x 8 x bfloat> @cvt1_bf16(<vscale x 16 x i8> %s) {
8+
; CHECK-LABEL: cvt1_bf16:
9+
; CHECK: // %bb.0:
10+
; CHECK-NEXT: bf1cvt z0.h, z0.b
11+
; CHECK-NEXT: ret
12+
%r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %s)
13+
ret <vscale x 8 x bfloat> %r
14+
}
15+
16+
define <vscale x 8 x bfloat> @cvt2_bf16(<vscale x 16 x i8> %s) {
17+
; CHECK-LABEL: cvt2_bf16:
18+
; CHECK: // %bb.0:
19+
; CHECK-NEXT: bf2cvt z0.h, z0.b
20+
; CHECK-NEXT: ret
21+
%r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %s)
22+
ret <vscale x 8 x bfloat> %r
23+
}
24+
25+
define <vscale x 8 x bfloat> @cvtlt1_bf16(<vscale x 16 x i8> %s) {
26+
; CHECK-LABEL: cvtlt1_bf16:
27+
; CHECK: // %bb.0:
28+
; CHECK-NEXT: bf1cvtlt z0.h, z0.b
29+
; CHECK-NEXT: ret
30+
%r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %s)
31+
ret <vscale x 8 x bfloat> %r
32+
}
33+
34+
define <vscale x 8 x bfloat> @cvtlt2_bf16(<vscale x 16 x i8> %s) {
35+
; CHECK-LABEL: cvtlt2_bf16:
36+
; CHECK: // %bb.0:
37+
; CHECK-NEXT: bf2cvtlt z0.h, z0.b
38+
; CHECK-NEXT: ret
39+
%r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %s)
40+
ret <vscale x 8 x bfloat> %r
41+
}
42+
43+
define <vscale x 8 x half> @cvt1_f16(<vscale x 16 x i8> %s) {
44+
; CHECK-LABEL: cvt1_f16:
45+
; CHECK: // %bb.0:
46+
; CHECK-NEXT: f1cvt z0.h, z0.b
47+
; CHECK-NEXT: ret
48+
%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %s)
49+
ret <vscale x 8 x half> %r
50+
}
51+
52+
define <vscale x 8 x half> @cvt2_f16(<vscale x 16 x i8> %s) {
53+
; CHECK-LABEL: cvt2_f16:
54+
; CHECK: // %bb.0:
55+
; CHECK-NEXT: f2cvt z0.h, z0.b
56+
; CHECK-NEXT: ret
57+
%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %s)
58+
ret <vscale x 8 x half> %r
59+
}
60+
61+
62+
define <vscale x 8 x half> @cvtlt1_f16(<vscale x 16 x i8> %s) {
63+
; CHECK-LABEL: cvtlt1_f16:
64+
; CHECK: // %bb.0:
65+
; CHECK-NEXT: f1cvtlt z0.h, z0.b
66+
; CHECK-NEXT: ret
67+
%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %s)
68+
ret <vscale x 8 x half> %r
69+
}
70+
71+
define <vscale x 8 x half> @cvtlt2_f16(<vscale x 16 x i8> %s) {
72+
; CHECK-LABEL: cvtlt2_f16:
73+
; CHECK: // %bb.0:
74+
; CHECK-NEXT: f2cvtlt z0.h, z0.b
75+
; CHECK-NEXT: ret
76+
%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %s)
77+
ret <vscale x 8 x half> %r
78+
}

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