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spallspall
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make clang format happy
1 parent 5836394 commit 3abd4c7

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3 files changed

+71
-69
lines changed

3 files changed

+71
-69
lines changed

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18880,7 +18880,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
1888018880
Value *X = EmitScalarExpr(E->getArg(0));
1888118881

1888218882
return Builder.CreateIntrinsic(
18883-
/*ReturnType=*/ConvertType(E->getType()),
18883+
/*ReturnType=*/ConvertType(E->getType()),
1888418884
getFirstBitHighIntrinsic(CGM.getHLSLRuntime(), E->getArg(0)->getType()),
1888518885
ArrayRef<Value *>{X}, nullptr, "hlsl.firstbithigh");
1888618886
}

‎clang/lib/Sema/SemaHLSL.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1959,7 +1959,8 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
19591959

19601960
if (auto *VecTy = EltTy->getAs<VectorType>()) {
19611961
EltTy = VecTy->getElementType();
1962-
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(), VecTy->getVectorKind());
1962+
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(),
1963+
VecTy->getVectorKind());
19631964
}
19641965

19651966
if (!EltTy->isIntegerType()) {

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 68 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -93,24 +93,24 @@ class SPIRVInstructionSelector : public InstructionSelector {
9393
MachineInstr &I) const;
9494

9595
bool selectFirstBitHigh(Register ResVReg, const SPIRVType *ResType,
96-
MachineInstr &I, bool IsSigned) const;
96+
MachineInstr &I, bool IsSigned) const;
9797

9898
bool selectFirstBitHigh16(Register ResVReg, const SPIRVType *ResType,
99-
MachineInstr &I, bool IsSigned) const;
99+
MachineInstr &I, bool IsSigned) const;
100100

101101
bool selectFirstBitHigh32(Register ResVReg, const SPIRVType *ResType,
102-
MachineInstr &I, Register SrcReg,
103-
bool IsSigned) const;
102+
MachineInstr &I, Register SrcReg,
103+
bool IsSigned) const;
104104

105105
bool selectFirstBitHigh64(Register ResVReg, const SPIRVType *ResType,
106-
MachineInstr &I, bool IsSigned) const;
106+
MachineInstr &I, bool IsSigned) const;
107107

108108
bool selectGlobalValue(Register ResVReg, MachineInstr &I,
109109
const MachineInstr *Init = nullptr) const;
110110

111111
bool selectNAryOpWithSrcs(Register ResVReg, const SPIRVType *ResType,
112-
MachineInstr &I, std::vector<Register> SrcRegs,
113-
unsigned Opcode) const;
112+
MachineInstr &I, std::vector<Register> SrcRegs,
113+
unsigned Opcode) const;
114114

115115
bool selectUnOpWithSrc(Register ResVReg, const SPIRVType *ResType,
116116
MachineInstr &I, Register SrcReg,
@@ -844,14 +844,14 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
844844
}
845845

846846
bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg,
847-
const SPIRVType *ResType,
848-
MachineInstr &I,
849-
std::vector<Register> Srcs,
850-
unsigned Opcode) const {
847+
const SPIRVType *ResType,
848+
MachineInstr &I,
849+
std::vector<Register> Srcs,
850+
unsigned Opcode) const {
851851
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
852-
.addDef(ResVReg)
853-
.addUse(GR.getSPIRVTypeID(ResType));
854-
for(Register SReg : Srcs) {
852+
.addDef(ResVReg)
853+
.addUse(GR.getSPIRVTypeID(ResType));
854+
for (Register SReg : Srcs) {
855855
MIB.addUse(SReg);
856856
}
857857
return MIB.constrainAllUses(TII, TRI, RBI);
@@ -2832,46 +2832,46 @@ Register SPIRVInstructionSelector::buildPointerToResource(
28322832
}
28332833

28342834
bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
2835-
const SPIRVType *ResType,
2836-
MachineInstr &I,
2837-
bool IsSigned) const {
2835+
const SPIRVType *ResType,
2836+
MachineInstr &I,
2837+
bool IsSigned) const {
28382838
unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
28392839
// zero or sign extend
28402840
Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
2841-
bool Result = selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(),
2842-
Opcode);
2841+
bool Result =
2842+
selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(), Opcode);
28432843
return Result & selectFirstBitHigh32(ResVReg, ResType, I, ExtReg, IsSigned);
28442844
}
28452845

28462846
bool SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
2847-
const SPIRVType *ResType,
2848-
MachineInstr &I,
2849-
Register SrcReg,
2850-
bool IsSigned) const {
2847+
const SPIRVType *ResType,
2848+
MachineInstr &I,
2849+
Register SrcReg,
2850+
bool IsSigned) const {
28512851
unsigned Opcode = IsSigned ? GL::FindSMsb : GL::FindUMsb;
28522852
return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
2853-
.addDef(ResVReg)
2854-
.addUse(GR.getSPIRVTypeID(ResType))
2855-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2856-
.addImm(Opcode)
2857-
.addUse(SrcReg)
2858-
.constrainAllUses(TII, TRI, RBI);
2853+
.addDef(ResVReg)
2854+
.addUse(GR.getSPIRVTypeID(ResType))
2855+
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2856+
.addImm(Opcode)
2857+
.addUse(SrcReg)
2858+
.constrainAllUses(TII, TRI, RBI);
28592859
}
28602860

28612861
bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
2862-
const SPIRVType *ResType,
2863-
MachineInstr &I,
2864-
bool IsSigned) const {
2862+
const SPIRVType *ResType,
2863+
MachineInstr &I,
2864+
bool IsSigned) const {
28652865
Register OpReg = I.getOperand(2).getReg();
28662866
// 1. split our int64 into 2 pieces using a bitcast
28672867
unsigned count = GR.getScalarOrVectorComponentCount(ResType);
28682868
SPIRVType *baseType = GR.retrieveScalarOrVectorIntType(ResType);
28692869
MachineIRBuilder MIRBuilder(I);
2870-
SPIRVType *postCastT = GR.getOrCreateSPIRVVectorType(baseType, 2 * count,
2871-
MIRBuilder);
2870+
SPIRVType *postCastT =
2871+
GR.getOrCreateSPIRVVectorType(baseType, 2 * count, MIRBuilder);
28722872
Register bitcastReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
2873-
bool Result = selectUnOpWithSrc(bitcastReg, postCastT, I, OpReg,
2874-
SPIRV::OpBitcast);
2873+
bool Result =
2874+
selectUnOpWithSrc(bitcastReg, postCastT, I, OpReg, SPIRV::OpBitcast);
28752875

28762876
// 2. call firstbithigh
28772877
Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
@@ -2889,76 +2889,77 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
28892889
// count should be one.
28902890

28912891
Register HighReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
2892-
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
2893-
TII.get(SPIRV::OpVectorShuffle))
2894-
.addDef(HighReg)
2895-
.addUse(GR.getSPIRVTypeID(VResType))
2896-
.addUse(FBHReg)
2897-
.addUse(FBHReg); // this vector will not be selected from; could be empty
2892+
auto MIB =
2893+
BuildMI(*I.getParent(), I, I.getDebugLoc(),
2894+
TII.get(SPIRV::OpVectorShuffle))
2895+
.addDef(HighReg)
2896+
.addUse(GR.getSPIRVTypeID(VResType))
2897+
.addUse(FBHReg)
2898+
.addUse(
2899+
FBHReg); // this vector will not be selected from; could be empty
28982900
unsigned i;
2899-
for(i = 0; i < count*2; i += 2) {
2901+
for (i = 0; i < count * 2; i += 2) {
29002902
MIB.addImm(i);
29012903
}
29022904
Result &= MIB.constrainAllUses(TII, TRI, RBI);
29032905

29042906
// get low bits
29052907
Register LowReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
2906-
MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
2907-
TII.get(SPIRV::OpVectorShuffle))
2908-
.addDef(LowReg)
2909-
.addUse(GR.getSPIRVTypeID(VResType))
2910-
.addUse(FBHReg)
2911-
.addUse(FBHReg); // this vector will not be selected from; could be empty
2912-
for(i = 1; i < count*2; i += 2) {
2908+
MIB =
2909+
BuildMI(*I.getParent(), I, I.getDebugLoc(),
2910+
TII.get(SPIRV::OpVectorShuffle))
2911+
.addDef(LowReg)
2912+
.addUse(GR.getSPIRVTypeID(VResType))
2913+
.addUse(FBHReg)
2914+
.addUse(
2915+
FBHReg); // this vector will not be selected from; could be empty
2916+
for (i = 1; i < count * 2; i += 2) {
29132917
MIB.addImm(i);
29142918
}
29152919
Result &= MIB.constrainAllUses(TII, TRI, RBI);
29162920

2917-
SPIRVType *BoolType =
2918-
GR.getOrCreateSPIRVVectorType(GR.getOrCreateSPIRVBoolType(I, TII),
2919-
count,
2920-
MIRBuilder);
2921+
SPIRVType *BoolType = GR.getOrCreateSPIRVVectorType(
2922+
GR.getOrCreateSPIRVBoolType(I, TII), count, MIRBuilder);
29212923
// check if the high bits are == -1;
29222924
Register NegOneReg = GR.getOrCreateConstVector(-1, I, VResType, TII);
29232925
// true if -1
29242926
Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
29252927
Result &= selectNAryOpWithSrcs(BReg, BoolType, I, {HighReg, NegOneReg},
2926-
SPIRV::OpIEqual);
2928+
SPIRV::OpIEqual);
29272929

29282930
// Select low bits if true in BReg, otherwise high bits
29292931
Register TmpReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
29302932
Result &= selectNAryOpWithSrcs(TmpReg, VResType, I, {BReg, LowReg, HighReg},
2931-
SPIRV::OpSelectVIVCond);
2933+
SPIRV::OpSelectVIVCond);
29322934

29332935
// Add 32 for high bits, 0 for low bits
29342936
Register ValReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
29352937
bool ZeroAsNull = STI.isOpenCLEnv();
29362938
Register Reg32 = GR.getOrCreateConstVector(32, I, VResType, TII, ZeroAsNull);
29372939
Register Reg0 = GR.getOrCreateConstVector(0, I, VResType, TII, ZeroAsNull);
29382940
Result &= selectNAryOpWithSrcs(ValReg, VResType, I, {BReg, Reg0, Reg32},
2939-
SPIRV::OpSelectVIVCond);
2941+
SPIRV::OpSelectVIVCond);
29402942

29412943
Register AddReg = ResVReg;
2942-
if(isScalarRes)
2944+
if (isScalarRes)
29432945
AddReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
29442946
Result &= selectNAryOpWithSrcs(AddReg, VResType, I, {ValReg, TmpReg},
2945-
SPIRV::OpIAddV);
2947+
SPIRV::OpIAddV);
29462948

29472949
// convert result back to scalar if necessary
29482950
if (!isScalarRes)
29492951
return Result;
29502952
else
2951-
return Result & selectNAryOpWithSrcs(ResVReg, ResType, I,
2952-
{AddReg,
2953-
GR.getOrCreateConstInt(0, I, ResType,
2954-
TII)},
2955-
SPIRV::OpVectorExtractDynamic);
2953+
return Result & selectNAryOpWithSrcs(
2954+
ResVReg, ResType, I,
2955+
{AddReg, GR.getOrCreateConstInt(0, I, ResType, TII)},
2956+
SPIRV::OpVectorExtractDynamic);
29562957
}
29572958

29582959
bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
2959-
const SPIRVType *ResType,
2960-
MachineInstr &I,
2961-
bool IsSigned) const {
2960+
const SPIRVType *ResType,
2961+
MachineInstr &I,
2962+
bool IsSigned) const {
29622963
// FindUMsb intrinsic only supports 32 bit integers
29632964
Register OpReg = I.getOperand(2).getReg();
29642965
SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpReg);

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