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Yeting Kuo
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[VP][RISCV] Introduce vp.lrint/llrint and RISC-V support.
RISC-V implements vector lrint/llrint by vfcvt.x.f.v.
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‎llvm/docs/LangRef.rst

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@@ -15990,6 +15990,8 @@ functions would, but without setting errno. If the rounded value is
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too large to be stored in the result type, the return value is a
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non-deterministic value (equivalent to `freeze poison`).
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.. _int_lrint:
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'``llvm.lrint.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -16035,6 +16037,8 @@ would, but without setting errno. If the rounded value is too large to
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be stored in the result type, the return value is a non-deterministic
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value (equivalent to `freeze poison`).
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.. _int_llrint:
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'``llvm.llrint.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -23344,6 +23348,101 @@ Examples:
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%t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a)
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%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> poison
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.. _int_vp_lrint:
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'``llvm.vp.lrint.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <16 x i32> @llvm.vp.lrint..v16i32.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
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declare <vscale x 4 x i32> @llvm.vp.lrint.nxv4i32.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
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declare <256 x i64> @llvm.vp.lrint.v256i64.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
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Overview:
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"""""""""
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Predicated lrint of a vector of floating-point values.
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Arguments:
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""""""""""
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The result is an intger vector and the first operand is an float vector and has
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the same number of elements as the result vector type. The second operand is the
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vector mask and has the same number of elements as the result vector type. The
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third operand is the explicit vector length of the operation.
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Semantics:
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""""""""""
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The '``llvm.vp.lrint``' intrinsic performs lrint (:ref:`lrint <int_lrint>`) of
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the first vector operand on each enabled lane. The result on disabled lanes is a
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:ref:`poison value <poisonvalues>`.
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Examples:
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"""""""""
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.. code-block:: llvm
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%r = call <4 x i32> @llvm.vp.lrint.v4i32.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
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;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
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%t = call <4 x i32> @llvm.lrint.v4f32(<4 x float> %a)
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%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
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.. _int_vp_llrint:
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'``llvm.vp.llrint.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <16 x i32> @llvm.vp.llrint..v16i32.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
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declare <vscale x 4 x i32> @llvm.vp.llrint.nxv4i32.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
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declare <256 x i64> @llvm.vp.llrint.v256i64.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
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Overview:
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"""""""""
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Predicated llrint of a vector of floating-point values.
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Arguments:
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""""""""""
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The result is an intger vector and the first operand is an float vector and has
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the same number of elements as the result vector type. The second operand is the
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vector mask and has the same number of elements as the result vector type. The
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third operand is the explicit vector length of the operation.
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Semantics:
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""""""""""
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The '``llvm.vp.llrint``' intrinsic performs lrint (:ref:`llrint <int_llrint>`) of
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the first vector operand on each enabled lane. The result on disabled lanes is a
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:ref:`poison value <poisonvalues>`.
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Examples:
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"""""""""
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.. code-block:: llvm
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%r = call <4 x i32> @llvm.vp.llrint.v4i32.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
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;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
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%t = call <4 x i32> @llvm.llrint.v4f32(<4 x float> %a)
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%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
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.. _int_vp_bitreverse:
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'``llvm.vp.bitreverse.*``' Intrinsics

‎llvm/include/llvm/IR/Intrinsics.td

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@@ -2036,6 +2036,14 @@ let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in {
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[ LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_lrint : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
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[ llvm_anyvector_ty,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_llrint : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
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[ llvm_anyvector_ty,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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// Casts
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def int_vp_trunc : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],

‎llvm/include/llvm/IR/VPIntrinsics.def

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@@ -437,6 +437,18 @@ VP_PROPERTY_FUNCTIONAL_INTRINSIC(nearbyint)
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VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT)
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END_REGISTER_VP(vp_nearbyint, VP_FNEARBYINT)
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// llvm.vp.lrint(x,mask,vlen)
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BEGIN_REGISTER_VP(vp_lrint, 1, 2, VP_LRINT, 0)
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VP_PROPERTY_FUNCTIONAL_INTRINSIC(lrint)
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VP_PROPERTY_FUNCTIONAL_SDOPC(LRINT)
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END_REGISTER_VP(vp_lrint, VP_LRINT)
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// llvm.vp.llrint(x,mask,vlen)
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BEGIN_REGISTER_VP(vp_llrint, 1, 2, VP_LLRINT, 0)
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VP_PROPERTY_FUNCTIONAL_INTRINSIC(llrint)
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VP_PROPERTY_FUNCTIONAL_SDOPC(LLRINT)
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END_REGISTER_VP(vp_llrint, VP_LLRINT)
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///// } Floating-Point Arithmetic
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///// Type Casts {

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

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@@ -1102,7 +1102,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::FRINT:
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case ISD::VP_FRINT:
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case ISD::LRINT:
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case ISD::VP_LRINT:
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case ISD::LLRINT:
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case ISD::VP_LLRINT:
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case ISD::FROUND:
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case ISD::VP_FROUND:
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case ISD::FROUNDEVEN:
@@ -4263,6 +4265,8 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::LRINT:
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case ISD::LLRINT:
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case ISD::VP_LRINT:
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case ISD::VP_LLRINT:
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Res = WidenVecRes_XRINT(N);
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break;
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@@ -4869,7 +4873,15 @@ SDValue DAGTypeLegalizer::WidenVecRes_XRINT(SDNode *N) {
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if (WidenNumElts != SrcVT.getVectorElementCount())
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return DAG.UnrollVectorOp(N, WidenNumElts.getKnownMinValue());
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return DAG.getNode(N->getOpcode(), dl, WidenVT, Src);
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if (N->getNumOperands() == 1)
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return DAG.getNode(N->getOpcode(), dl, WidenVT, Src);
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assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
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assert(N->isVPOpcode() && "Expected VP opcode");
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SDValue Mask =
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GetWidenedMask(N->getOperand(1), WidenVT.getVectorElementCount());
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return DAG.getNode(N->getOpcode(), dl, WidenVT, Src, Mask, N->getOperand(2));
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}
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SDValue DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -699,7 +699,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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ISD::VP_FCEIL, ISD::VP_FFLOOR, ISD::VP_FROUND,
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ISD::VP_FROUNDEVEN, ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO,
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ISD::VP_FRINT, ISD::VP_FNEARBYINT, ISD::VP_IS_FPCLASS,
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ISD::VP_FMINIMUM, ISD::VP_FMAXIMUM, ISD::EXPERIMENTAL_VP_REVERSE,
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ISD::VP_FMINIMUM, ISD::VP_FMAXIMUM, ISD::VP_LRINT,
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ISD::VP_LLRINT, ISD::EXPERIMENTAL_VP_REVERSE,
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ISD::EXPERIMENTAL_VP_SPLICE};
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static const unsigned IntegerVecReduceOps[] = {
@@ -5690,6 +5691,9 @@ static unsigned getRISCVVLOp(SDValue Op) {
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switch (Op.getOpcode()) {
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default:
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llvm_unreachable("don't have RISC-V specified VL op for this SDNode");
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case ISD::VP_LRINT:
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case ISD::VP_LLRINT:
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return RISCVISD::VFCVT_X_F_VL;
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OP_CASE(ADD)
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OP_CASE(SUB)
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OP_CASE(MUL)
@@ -6793,6 +6797,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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case ISD::VP_UDIV:
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case ISD::VP_SREM:
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case ISD::VP_UREM:
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case ISD::VP_LRINT:
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case ISD::VP_LLRINT:
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return lowerVPOp(Op, DAG);
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case ISD::VP_AND:
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case ISD::VP_OR:

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