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[LiveIntervals] Ignore artificial regs when adding kill flags
If parts of a physical register for a given liverange, as assigned by the register allocator, can be used to store other values not represented by this liverange, then `LiveIntervals::addKillFlags` normally avoids adding a kill flag on the use of this register when the value's liverange ends. However, if all the other regunits are artificial, then we can still safely add the kill flag, since those parts of the register can never be accessed independently.
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lines changed

4 files changed

+84
-68
lines changed

‎llvm/lib/CodeGen/LiveIntervals.cpp

Lines changed: 37 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -710,6 +710,30 @@ void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
710710
// Register allocator hooks.
711711
//
712712

713+
/// Returns true if the physreg has multiple regunits that can be accessed
714+
/// as independent registers.
715+
///
716+
/// Returns 'true' for e.g.:
717+
/// gpr64_0_gpr64_1
718+
// => two independently accessible registers gpr64_0 and gpr64_1.
719+
///
720+
/// Returns 'false' for e.g.:
721+
/// gpr64_0: => accessible register, reads/writes 64bits
722+
/// gpr32_0: => accessible sub-regsiter of gpr64_0, reads/writes 32bits
723+
// gpr32_0_hi => top 32bits of gpr64_0, not independently accessible.
724+
static bool hasMultipleAddressableRegUnits(const TargetRegisterInfo *TRI,
725+
MCPhysReg PhysReg) {
726+
unsigned NumAddressableRegUnits = 0;
727+
for (MCRegUnit U : TRI->regunits(PhysReg)) {
728+
for (MCRegUnitRootIterator RI(U, TRI); RI.isValid(); ++RI)
729+
if (!TRI->isArtificial(*RI) && TRI->isInAllocatableClass(*RI))
730+
NumAddressableRegUnits++;
731+
if (NumAddressableRegUnits > 1)
732+
return true;
733+
}
734+
return false;
735+
}
736+
713737
void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
714738
// Keep track of regunit ranges.
715739
SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
@@ -736,6 +760,18 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
736760
continue;
737761
RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
738762
}
763+
764+
// If parts of a physical register for a given liverange, as assigned by the
765+
// register allocator, can be used to store other values not represented by
766+
// this liverange, then `LiveIntervals::addKillFlags` normally avoids adding
767+
// a kill flag on the use of this register when the value's liverange ends.
768+
//
769+
// However, if all the other regunits are artificial, then we can still
770+
// safely add the kill flag, since those parts of the register can never be
771+
// accessed independently.
772+
bool AssumeOtherUnitsCanBeUsed =
773+
hasMultipleAddressableRegUnits(TRI, PhysReg);
774+
739775
// Every instruction that kills Reg corresponds to a segment range end
740776
// point.
741777
for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
@@ -780,7 +816,7 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
780816
// are actually never written by %2. After assignment the <kill>
781817
// flag at the read instruction is invalid.
782818
LaneBitmask DefinedLanesMask;
783-
if (LI.hasSubRanges()) {
819+
if (LI.hasSubRanges() && AssumeOtherUnitsCanBeUsed) {
784820
// Compute a mask of lanes that are defined.
785821
DefinedLanesMask = LaneBitmask::getNone();
786822
for (const LiveInterval::SubRange &SR : LI.subranges())

‎llvm/test/CodeGen/AArch64/arm64-addrmode.ll

Lines changed: 40 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -214,9 +214,8 @@ define void @t17(i64 %a) {
214214
define i8 @LdOffset_i8(ptr %a) {
215215
; CHECK-LABEL: LdOffset_i8:
216216
; CHECK: // %bb.0:
217-
; CHECK-NEXT: mov w8, #56952 // =0xde78
218-
; CHECK-NEXT: movk w8, #15, lsl #16
219-
; CHECK-NEXT: ldrb w0, [x0, x8]
217+
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
218+
; CHECK-NEXT: ldrb w0, [x8, #3704]
220219
; CHECK-NEXT: ret
221220
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
222221
%val = load i8, ptr %arrayidx, align 1
@@ -227,9 +226,8 @@ define i8 @LdOffset_i8(ptr %a) {
227226
define i32 @LdOffset_i8_zext32(ptr %a) {
228227
; CHECK-LABEL: LdOffset_i8_zext32:
229228
; CHECK: // %bb.0:
230-
; CHECK-NEXT: mov w8, #56952 // =0xde78
231-
; CHECK-NEXT: movk w8, #15, lsl #16
232-
; CHECK-NEXT: ldrb w0, [x0, x8]
229+
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
230+
; CHECK-NEXT: ldrb w0, [x8, #3704]
233231
; CHECK-NEXT: ret
234232
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
235233
%val = load i8, ptr %arrayidx, align 1
@@ -241,9 +239,8 @@ define i32 @LdOffset_i8_zext32(ptr %a) {
241239
define i32 @LdOffset_i8_sext32(ptr %a) {
242240
; CHECK-LABEL: LdOffset_i8_sext32:
243241
; CHECK: // %bb.0:
244-
; CHECK-NEXT: mov w8, #56952 // =0xde78
245-
; CHECK-NEXT: movk w8, #15, lsl #16
246-
; CHECK-NEXT: ldrsb w0, [x0, x8]
242+
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
243+
; CHECK-NEXT: ldrsb w0, [x8, #3704]
247244
; CHECK-NEXT: ret
248245
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
249246
%val = load i8, ptr %arrayidx, align 1
@@ -255,9 +252,8 @@ define i32 @LdOffset_i8_sext32(ptr %a) {
255252
define i64 @LdOffset_i8_zext64(ptr %a) {
256253
; CHECK-LABEL: LdOffset_i8_zext64:
257254
; CHECK: // %bb.0:
258-
; CHECK-NEXT: mov w8, #56952 // =0xde78
259-
; CHECK-NEXT: movk w8, #15, lsl #16
260-
; CHECK-NEXT: ldrb w0, [x0, x8]
255+
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
256+
; CHECK-NEXT: ldrb w0, [x8, #3704]
261257
; CHECK-NEXT: ret
262258
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
263259
%val = load i8, ptr %arrayidx, align 1
@@ -269,9 +265,8 @@ define i64 @LdOffset_i8_zext64(ptr %a) {
269265
define i64 @LdOffset_i8_sext64(ptr %a) {
270266
; CHECK-LABEL: LdOffset_i8_sext64:
271267
; CHECK: // %bb.0:
272-
; CHECK-NEXT: mov w8, #56952 // =0xde78
273-
; CHECK-NEXT: movk w8, #15, lsl #16
274-
; CHECK-NEXT: ldrsb x0, [x0, x8]
268+
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
269+
; CHECK-NEXT: ldrsb x0, [x8, #3704]
275270
; CHECK-NEXT: ret
276271
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
277272
%val = load i8, ptr %arrayidx, align 1
@@ -283,9 +278,8 @@ define i64 @LdOffset_i8_sext64(ptr %a) {
283278
define i16 @LdOffset_i16(ptr %a) {
284279
; CHECK-LABEL: LdOffset_i16:
285280
; CHECK: // %bb.0:
286-
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
287-
; CHECK-NEXT: movk w8, #31, lsl #16
288-
; CHECK-NEXT: ldrh w0, [x0, x8]
281+
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
282+
; CHECK-NEXT: ldrh w0, [x8, #7408]
289283
; CHECK-NEXT: ret
290284
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
291285
%val = load i16, ptr %arrayidx, align 2
@@ -296,9 +290,8 @@ define i16 @LdOffset_i16(ptr %a) {
296290
define i32 @LdOffset_i16_zext32(ptr %a) {
297291
; CHECK-LABEL: LdOffset_i16_zext32:
298292
; CHECK: // %bb.0:
299-
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
300-
; CHECK-NEXT: movk w8, #31, lsl #16
301-
; CHECK-NEXT: ldrh w0, [x0, x8]
293+
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
294+
; CHECK-NEXT: ldrh w0, [x8, #7408]
302295
; CHECK-NEXT: ret
303296
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
304297
%val = load i16, ptr %arrayidx, align 2
@@ -310,9 +303,8 @@ define i32 @LdOffset_i16_zext32(ptr %a) {
310303
define i32 @LdOffset_i16_sext32(ptr %a) {
311304
; CHECK-LABEL: LdOffset_i16_sext32:
312305
; CHECK: // %bb.0:
313-
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
314-
; CHECK-NEXT: movk w8, #31, lsl #16
315-
; CHECK-NEXT: ldrsh w0, [x0, x8]
306+
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
307+
; CHECK-NEXT: ldrsh w0, [x8, #7408]
316308
; CHECK-NEXT: ret
317309
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
318310
%val = load i16, ptr %arrayidx, align 2
@@ -324,9 +316,8 @@ define i32 @LdOffset_i16_sext32(ptr %a) {
324316
define i64 @LdOffset_i16_zext64(ptr %a) {
325317
; CHECK-LABEL: LdOffset_i16_zext64:
326318
; CHECK: // %bb.0:
327-
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
328-
; CHECK-NEXT: movk w8, #31, lsl #16
329-
; CHECK-NEXT: ldrh w0, [x0, x8]
319+
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
320+
; CHECK-NEXT: ldrh w0, [x8, #7408]
330321
; CHECK-NEXT: ret
331322
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
332323
%val = load i16, ptr %arrayidx, align 2
@@ -338,9 +329,8 @@ define i64 @LdOffset_i16_zext64(ptr %a) {
338329
define i64 @LdOffset_i16_sext64(ptr %a) {
339330
; CHECK-LABEL: LdOffset_i16_sext64:
340331
; CHECK: // %bb.0:
341-
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
342-
; CHECK-NEXT: movk w8, #31, lsl #16
343-
; CHECK-NEXT: ldrsh x0, [x0, x8]
332+
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
333+
; CHECK-NEXT: ldrsh x0, [x8, #7408]
344334
; CHECK-NEXT: ret
345335
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
346336
%val = load i16, ptr %arrayidx, align 2
@@ -352,9 +342,8 @@ define i64 @LdOffset_i16_sext64(ptr %a) {
352342
define i32 @LdOffset_i32(ptr %a) {
353343
; CHECK-LABEL: LdOffset_i32:
354344
; CHECK: // %bb.0:
355-
; CHECK-NEXT: mov w8, #31200 // =0x79e0
356-
; CHECK-NEXT: movk w8, #63, lsl #16
357-
; CHECK-NEXT: ldr w0, [x0, x8]
345+
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
346+
; CHECK-NEXT: ldr w0, [x8, #14816]
358347
; CHECK-NEXT: ret
359348
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
360349
%val = load i32, ptr %arrayidx, align 4
@@ -365,9 +354,8 @@ define i32 @LdOffset_i32(ptr %a) {
365354
define i64 @LdOffset_i32_zext64(ptr %a) {
366355
; CHECK-LABEL: LdOffset_i32_zext64:
367356
; CHECK: // %bb.0:
368-
; CHECK-NEXT: mov w8, #31200 // =0x79e0
369-
; CHECK-NEXT: movk w8, #63, lsl #16
370-
; CHECK-NEXT: ldr w0, [x0, x8]
357+
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
358+
; CHECK-NEXT: ldr w0, [x8, #14816]
371359
; CHECK-NEXT: ret
372360
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
373361
%val = load i32, ptr %arrayidx, align 2
@@ -379,9 +367,8 @@ define i64 @LdOffset_i32_zext64(ptr %a) {
379367
define i64 @LdOffset_i32_sext64(ptr %a) {
380368
; CHECK-LABEL: LdOffset_i32_sext64:
381369
; CHECK: // %bb.0:
382-
; CHECK-NEXT: mov w8, #31200 // =0x79e0
383-
; CHECK-NEXT: movk w8, #63, lsl #16
384-
; CHECK-NEXT: ldrsw x0, [x0, x8]
370+
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
371+
; CHECK-NEXT: ldrsw x0, [x8, #14816]
385372
; CHECK-NEXT: ret
386373
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
387374
%val = load i32, ptr %arrayidx, align 2
@@ -393,9 +380,8 @@ define i64 @LdOffset_i32_sext64(ptr %a) {
393380
define i64 @LdOffset_i64(ptr %a) {
394381
; CHECK-LABEL: LdOffset_i64:
395382
; CHECK: // %bb.0:
396-
; CHECK-NEXT: mov w8, #62400 // =0xf3c0
397-
; CHECK-NEXT: movk w8, #126, lsl #16
398-
; CHECK-NEXT: ldr x0, [x0, x8]
383+
; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
384+
; CHECK-NEXT: ldr x0, [x8, #29632]
399385
; CHECK-NEXT: ret
400386
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
401387
%val = load i64, ptr %arrayidx, align 4
@@ -406,9 +392,8 @@ define i64 @LdOffset_i64(ptr %a) {
406392
define <2 x i32> @LdOffset_v2i32(ptr %a) {
407393
; CHECK-LABEL: LdOffset_v2i32:
408394
; CHECK: // %bb.0:
409-
; CHECK-NEXT: mov w8, #62400 // =0xf3c0
410-
; CHECK-NEXT: movk w8, #126, lsl #16
411-
; CHECK-NEXT: ldr d0, [x0, x8]
395+
; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
396+
; CHECK-NEXT: ldr d0, [x8, #29632]
412397
; CHECK-NEXT: ret
413398
%arrayidx = getelementptr inbounds <2 x i32>, ptr %a, i64 1039992
414399
%val = load <2 x i32>, ptr %arrayidx, align 4
@@ -419,9 +404,8 @@ define <2 x i32> @LdOffset_v2i32(ptr %a) {
419404
define <2 x i64> @LdOffset_v2i64(ptr %a) {
420405
; CHECK-LABEL: LdOffset_v2i64:
421406
; CHECK: // %bb.0:
422-
; CHECK-NEXT: mov w8, #59264 // =0xe780
423-
; CHECK-NEXT: movk w8, #253, lsl #16
424-
; CHECK-NEXT: ldr q0, [x0, x8]
407+
; CHECK-NEXT: add x8, x0, #4048, lsl #12 // =16580608
408+
; CHECK-NEXT: ldr q0, [x8, #59264]
425409
; CHECK-NEXT: ret
426410
%arrayidx = getelementptr inbounds <2 x i64>, ptr %a, i64 1039992
427411
%val = load <2 x i64>, ptr %arrayidx, align 4
@@ -432,9 +416,8 @@ define <2 x i64> @LdOffset_v2i64(ptr %a) {
432416
define double @LdOffset_i8_f64(ptr %a) {
433417
; CHECK-LABEL: LdOffset_i8_f64:
434418
; CHECK: // %bb.0:
435-
; CHECK-NEXT: mov w8, #56952 // =0xde78
436-
; CHECK-NEXT: movk w8, #15, lsl #16
437-
; CHECK-NEXT: ldrsb w8, [x0, x8]
419+
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
420+
; CHECK-NEXT: ldrsb w8, [x8, #3704]
438421
; CHECK-NEXT: scvtf d0, w8
439422
; CHECK-NEXT: ret
440423
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
@@ -447,9 +430,8 @@ define double @LdOffset_i8_f64(ptr %a) {
447430
define double @LdOffset_i16_f64(ptr %a) {
448431
; CHECK-LABEL: LdOffset_i16_f64:
449432
; CHECK: // %bb.0:
450-
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
451-
; CHECK-NEXT: movk w8, #31, lsl #16
452-
; CHECK-NEXT: ldrsh w8, [x0, x8]
433+
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
434+
; CHECK-NEXT: ldrsh w8, [x8, #7408]
453435
; CHECK-NEXT: scvtf d0, w8
454436
; CHECK-NEXT: ret
455437
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
@@ -462,9 +444,8 @@ define double @LdOffset_i16_f64(ptr %a) {
462444
define double @LdOffset_i32_f64(ptr %a) {
463445
; CHECK-LABEL: LdOffset_i32_f64:
464446
; CHECK: // %bb.0:
465-
; CHECK-NEXT: mov w8, #31200 // =0x79e0
466-
; CHECK-NEXT: movk w8, #63, lsl #16
467-
; CHECK-NEXT: ldr s0, [x0, x8]
447+
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
448+
; CHECK-NEXT: ldr s0, [x8, #14816]
468449
; CHECK-NEXT: ucvtf d0, d0
469450
; CHECK-NEXT: ret
470451
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
@@ -477,9 +458,8 @@ define double @LdOffset_i32_f64(ptr %a) {
477458
define double @LdOffset_i64_f64(ptr %a) {
478459
; CHECK-LABEL: LdOffset_i64_f64:
479460
; CHECK: // %bb.0:
480-
; CHECK-NEXT: mov w8, #62400 // =0xf3c0
481-
; CHECK-NEXT: movk w8, #126, lsl #16
482-
; CHECK-NEXT: ldr d0, [x0, x8]
461+
; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
462+
; CHECK-NEXT: ldr d0, [x8, #29632]
483463
; CHECK-NEXT: scvtf d0, d0
484464
; CHECK-NEXT: ret
485465
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992

‎llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,7 @@ body: |
220220
; CHECK-NEXT: {{ $}}
221221
; CHECK-NEXT: STRXui renamable $x8, %stack.1, 0 :: (store (s64) into %stack.1)
222222
; CHECK-NEXT: renamable $w9 = MOVi32imm 36
223-
; CHECK-NEXT: renamable $x8 = MADDXrrr killed renamable $x8, renamable $x9, $xzr
223+
; CHECK-NEXT: renamable $x8 = MADDXrrr killed renamable $x8, killed renamable $x9, $xzr
224224
; CHECK-NEXT: renamable $x9 = MOVaddr target-flags(aarch64-page) @g, target-flags(aarch64-pageoff, aarch64-nc) @g
225225
; CHECK-NEXT: renamable $w8 = LDRWroX killed renamable $x9, killed renamable $x8, 0, 0 :: (load (s32) from %ir.arrayidx9)
226226
; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w8, 1, 0, implicit-def $nzcv
@@ -245,7 +245,7 @@ body: |
245245
; CHECK-NEXT: liveins: $w10, $w11, $x2, $x12
246246
; CHECK-NEXT: {{ $}}
247247
; CHECK-NEXT: renamable $w8 = MOVi32imm 36
248-
; CHECK-NEXT: renamable $x8 = MADDXrrr renamable $x12, renamable $x8, $xzr
248+
; CHECK-NEXT: renamable $x8 = MADDXrrr renamable $x12, killed renamable $x8, $xzr
249249
; CHECK-NEXT: renamable $x9 = MOVaddr target-flags(aarch64-page) @g, target-flags(aarch64-pageoff, aarch64-nc) @g
250250
; CHECK-NEXT: renamable $w8 = LDRWroX killed renamable $x9, killed renamable $x8, 0, 0 :: (load (s32) from %ir.arrayidx14)
251251
; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w8, 1, 0, implicit-def $nzcv

‎llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -27,12 +27,11 @@ define i32 @caller() nounwind ssp {
2727
; CHECK-NEXT: sub sp, sp, #208
2828
; CHECK-NEXT: mov w8, #10 ; =0xa
2929
; CHECK-NEXT: mov w9, #9 ; =0x9
30-
; CHECK-NEXT: mov w0, #1 ; =0x1
30+
; CHECK-NEXT: mov w10, #8 ; =0x8
3131
; CHECK-NEXT: stp x9, x8, [sp, #24]
32-
; CHECK-NEXT: mov w8, #8 ; =0x8
33-
; CHECK-NEXT: mov w9, #6 ; =0x6
34-
; CHECK-NEXT: str x8, [sp, #16]
3532
; CHECK-NEXT: mov w8, #7 ; =0x7
33+
; CHECK-NEXT: mov w9, #6 ; =0x6
34+
; CHECK-NEXT: mov w0, #1 ; =0x1
3635
; CHECK-NEXT: mov w1, #2 ; =0x2
3736
; CHECK-NEXT: mov w2, #3 ; =0x3
3837
; CHECK-NEXT: mov w3, #4 ; =0x4
@@ -47,7 +46,8 @@ define i32 @caller() nounwind ssp {
4746
; CHECK-NEXT: stp x22, x21, [sp, #160] ; 16-byte Folded Spill
4847
; CHECK-NEXT: stp x20, x19, [sp, #176] ; 16-byte Folded Spill
4948
; CHECK-NEXT: stp x29, x30, [sp, #192] ; 16-byte Folded Spill
50-
; CHECK-NEXT: stp x9, x8, [sp]
49+
; CHECK-NEXT: stp x8, x10, [sp, #8]
50+
; CHECK-NEXT: str x9, [sp]
5151
; CHECK-NEXT: bl _callee
5252
; CHECK-NEXT: ldp x29, x30, [sp, #192] ; 16-byte Folded Reload
5353
; CHECK-NEXT: ldp x20, x19, [sp, #176] ; 16-byte Folded Reload

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