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[AMDGPU] Remove DPP DecoderNamespaces. NFC. (#82491)
Now that there is no special checking for valid DPP encodings, these instructions can use the same DecoderNamespace as other 64- or 96-bit instructions. Also clean up setting DecoderNamespace: in most cases it should be set as a pair with AssemblerPredicate.
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6 files changed

+288
-400
lines changed

6 files changed

+288
-400
lines changed

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 5 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -462,33 +462,13 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
462462
// encodings
463463
if (isGFX11Plus() && Bytes.size() >= 12 ) {
464464
DecoderUInt128 DecW = eat12Bytes(Bytes);
465-
Res =
466-
tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696,
467-
MI, DecW, Address, CS);
465+
Res = tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
466+
DecW, Address, CS);
468467
if (Res)
469468
break;
470469

471-
Res =
472-
tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696,
473-
MI, DecW, Address, CS);
474-
if (Res)
475-
break;
476-
477-
Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696,
478-
MI, DecW, Address, CS);
479-
if (Res)
480-
break;
481-
482-
Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696,
483-
MI, DecW, Address, CS);
484-
if (Res)
485-
break;
486-
487-
Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS);
488-
if (Res)
489-
break;
490-
491-
Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS);
470+
Res = tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
471+
DecW, Address, CS);
492472
if (Res)
493473
break;
494474

@@ -508,33 +488,6 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
508488
break;
509489
}
510490

511-
Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS);
512-
if (Res)
513-
break;
514-
515-
Res = tryDecodeInst(DecoderTableDPP8GFX1164,
516-
DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS);
517-
if (Res)
518-
break;
519-
520-
Res = tryDecodeInst(DecoderTableDPP8GFX1264,
521-
DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS);
522-
if (Res)
523-
break;
524-
525-
Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS);
526-
if (Res) break;
527-
528-
Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664,
529-
MI, QW, Address, CS);
530-
if (Res)
531-
break;
532-
533-
Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664,
534-
MI, QW, Address, CS);
535-
if (Res)
536-
break;
537-
538491
if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) {
539492
Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS);
540493
if (Res)
@@ -593,7 +546,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
593546
break;
594547
}
595548

596-
// Reinitialize Bytes as DPP64 could have eaten too much
549+
// Reinitialize Bytes
597550
Bytes = Bytes_.slice(0, MaxInstBytesNum);
598551

599552
// Try decode 32-bit instruction

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 34 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -749,7 +749,7 @@ class VOP1_DPP16<bits<8> op, VOP1_DPP_Pseudo ps, int subtarget, VOPProfile p = p
749749
class VOP1_DPP16_Gen<bits<8> op, VOP1_DPP_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :
750750
VOP1_DPP16 <op, ps, Gen.Subtarget, p> {
751751
let AssemblerPredicate = Gen.AssemblerPredicate;
752-
let DecoderNamespace = "DPP"#Gen.DecoderNamespace;
752+
let DecoderNamespace = Gen.DecoderNamespace;
753753
}
754754

755755
class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
@@ -770,7 +770,7 @@ class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
770770
class VOP1_DPP8_Gen<bits<8> op, VOP1_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :
771771
VOP1_DPP8<op, ps, p> {
772772
let AssemblerPredicate = Gen.AssemblerPredicate;
773-
let DecoderNamespace = "DPP8"#Gen.DecoderNamespace;
773+
let DecoderNamespace = Gen.DecoderNamespace;
774774
}
775775

776776
//===----------------------------------------------------------------------===//
@@ -816,7 +816,7 @@ multiclass VOP1_Real_dpp_with_name<GFXGen Gen, bits<9> op, string opName,
816816
string asmName> {
817817
defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
818818
let AsmString = asmName # ps.Pfl.AsmDPP16,
819-
DecoderNamespace = "DPP" # Gen.DecoderNamespace #
819+
DecoderNamespace = Gen.DecoderNamespace #
820820
!if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {
821821
defm NAME : VOP1_Real_dpp<Gen, op, opName>;
822822
}
@@ -831,7 +831,7 @@ multiclass VOP1_Real_dpp8_with_name<GFXGen Gen, bits<9> op, string opName,
831831
string asmName> {
832832
defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
833833
let AsmString = asmName # ps.Pfl.AsmDPP8,
834-
DecoderNamespace = "DPP8" # Gen.DecoderNamespace #
834+
DecoderNamespace = Gen.DecoderNamespace #
835835
!if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {
836836
defm NAME : VOP1_Real_dpp8<Gen, op, opName>;
837837
}
@@ -994,9 +994,7 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
994994
}
995995
multiclass VOP1_Real_dpp8_gfx10<bits<9> op> {
996996
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
997-
def _dpp8_gfx10 : VOP1_DPP8<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")> {
998-
let DecoderNamespace = "DPP8";
999-
}
997+
def _dpp8_gfx10 : VOP1_DPP8<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")>;
1000998
}
1001999
} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
10021000

@@ -1192,16 +1190,14 @@ class VOP1_DPPe <bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
11921190
let Inst{31-25} = 0x3f; //encoding
11931191
}
11941192

1195-
multiclass VOP1Only_Real_vi <bits<10> op> {
1196-
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1193+
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1194+
multiclass VOP1Only_Real_vi <bits<10> op> {
11971195
def _vi :
11981196
VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
11991197
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
12001198
}
1201-
}
12021199

1203-
multiclass VOP1_Real_e32e64_vi <bits<10> op> {
1204-
let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1200+
multiclass VOP1_Real_e32e64_vi <bits<10> op> {
12051201
def _e32_vi :
12061202
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
12071203
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
@@ -1389,44 +1385,41 @@ def : GCNPat <
13891385
// GFX9
13901386
//===----------------------------------------------------------------------===//
13911387

1392-
multiclass VOP1_Real_gfx9 <bits<10> op> {
1393-
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1388+
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1389+
multiclass VOP1_Real_gfx9 <bits<10> op> {
13941390
defm NAME : VOP1_Real_e32e64_vi <op>;
1395-
}
1396-
1397-
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
1398-
def _sdwa_gfx9 :
1399-
VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
1400-
VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1401-
1402-
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
1403-
def _dpp_gfx9 :
1404-
VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1405-
VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")>;
1406-
1407-
}
14081391

1409-
multiclass VOP1_Real_NoDstSel_SDWA_gfx9 <bits<10> op> {
1410-
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1411-
defm NAME : VOP1_Real_e32e64_vi <op>;
1392+
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
1393+
def _sdwa_gfx9 :
1394+
VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
1395+
VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1396+
1397+
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
1398+
def _dpp_gfx9 :
1399+
VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1400+
VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")>;
14121401
}
14131402

1414-
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
1415-
def _sdwa_gfx9 :
1416-
VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
1417-
VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1418-
let Inst{42-40} = 6;
1419-
}
1403+
multiclass VOP1_Real_NoDstSel_SDWA_gfx9 <bits<10> op> {
1404+
defm NAME : VOP1_Real_e32e64_vi <op>;
14201405

1421-
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
1422-
def _dpp_gfx9 :
1423-
VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1424-
VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")>;
1406+
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
1407+
def _sdwa_gfx9 :
1408+
VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
1409+
VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1410+
let Inst{42-40} = 6;
1411+
}
1412+
1413+
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
1414+
def _dpp_gfx9 :
1415+
VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1416+
VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")>;
1417+
}
14251418
}
14261419

14271420
defm V_SCREEN_PARTITION_4SE_B32 : VOP1_Real_gfx9 <0x37>;
14281421

1429-
let AssemblerPredicate = isGFX940Plus, DecoderNamespace = "GFX9" in
1422+
let AssemblerPredicate = isGFX940Plus in
14301423
defm V_MOV_B64 : VOP1_Real_gfx9 <0x38>;
14311424

14321425
let OtherPredicates = [HasFP8ConversionInsts] in {

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 11 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1273,7 +1273,7 @@ class VOP2_DPP16_Gen<bits<6> op, VOP2_DPP_Pseudo ps, GFXGen Gen,
12731273
VOP2_DPP16<op, ps, Gen.Subtarget, opName, p> {
12741274
let AssemblerPredicate = Gen.AssemblerPredicate;
12751275
let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []);
1276-
let DecoderNamespace = "DPP"#Gen.DecoderNamespace#
1276+
let DecoderNamespace = Gen.DecoderNamespace#
12771277
!if(ps.Pfl.IsRealTrue16, "", "_FAKE16");
12781278
}
12791279

@@ -1302,7 +1302,7 @@ class VOP2_DPP8_Gen<bits<6> op, VOP2_Pseudo ps, GFXGen Gen,
13021302
VOP2_DPP8<op, ps, p> {
13031303
let AssemblerPredicate = Gen.AssemblerPredicate;
13041304
let OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []);
1305-
let DecoderNamespace = "DPP8"#Gen.DecoderNamespace#
1305+
let DecoderNamespace = Gen.DecoderNamespace#
13061306
!if(ps.Pfl.IsRealTrue16, "", "_FAKE16");
13071307
}
13081308

@@ -1748,9 +1748,7 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
17481748
}
17491749
multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
17501750
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
1751-
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
1752-
let DecoderNamespace = "DPP8";
1753-
}
1751+
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
17541752
}
17551753

17561754
//===------------------------- VOP2 (with name) -------------------------===//
@@ -1797,7 +1795,6 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
17971795
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
17981796
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
17991797
let AsmString = asmName # ps.Pfl.AsmDPP8;
1800-
let DecoderNamespace = "DPP8";
18011798
}
18021799
}
18031800

@@ -1876,7 +1873,6 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
18761873
VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
18771874
string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
18781875
let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1879-
let DecoderNamespace = "DPP8";
18801876
}
18811877
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
18821878
def _dpp8_w32_gfx10 :
@@ -2231,22 +2227,20 @@ multiclass VOP2_SDWA9_Real <bits<6> op> {
22312227
VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
22322228
}
22332229

2234-
let AssemblerPredicate = isGFX8Only in {
2230+
let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in {
22352231

22362232
multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
22372233
def _e32_vi :
22382234
VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
22392235
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
22402236
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
22412237
let AsmString = AsmName # ps.AsmOperands;
2242-
let DecoderNamespace = "GFX8";
22432238
}
22442239
def _e64_vi :
22452240
VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
22462241
VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
22472242
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
22482243
let AsmString = AsmName # ps.AsmOperands;
2249-
let DecoderNamespace = "GFX8";
22502244
}
22512245
if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA then
22522246
def _sdwa_vi :
@@ -2263,24 +2257,23 @@ multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName
22632257
let AsmString = AsmName # ps.AsmOperands;
22642258
}
22652259
}
2266-
}
22672260

2268-
let AssemblerPredicate = isGFX9Only in {
2261+
} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8"
2262+
2263+
let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
22692264

22702265
multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
22712266
def _e32_gfx9 :
22722267
VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
22732268
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
22742269
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
22752270
let AsmString = AsmName # ps.AsmOperands;
2276-
let DecoderNamespace = "GFX9";
22772271
}
22782272
def _e64_gfx9 :
22792273
VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
22802274
VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
22812275
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
22822276
let AsmString = AsmName # ps.AsmOperands;
2283-
let DecoderNamespace = "GFX9";
22842277
}
22852278
if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9 then
22862279
def _sdwa_gfx9 :
@@ -2295,21 +2288,16 @@ multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
22952288
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
22962289
VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
22972290
let AsmString = AsmName # ps.AsmOperands;
2298-
let DecoderNamespace = "GFX9";
22992291
}
23002292
}
23012293

23022294
multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
23032295
def _e32_gfx9 :
23042296
VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
2305-
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
2306-
let DecoderNamespace = "GFX9";
2307-
}
2297+
VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
23082298
def _e64_gfx9 :
23092299
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
2310-
VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
2311-
let DecoderNamespace = "GFX9";
2312-
}
2300+
VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
23132301
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
23142302
def _sdwa_gfx9 :
23152303
VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
@@ -2318,12 +2306,10 @@ multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
23182306
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then
23192307
def _dpp_gfx9 :
23202308
VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
2321-
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
2322-
let DecoderNamespace = "GFX9";
2323-
}
2309+
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
23242310
}
23252311

2326-
} // AssemblerPredicate = isGFX9Only
2312+
} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
23272313

23282314
multiclass VOP2_Real_e32e64_vi <bits<6> op> :
23292315
Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {

‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1486,7 +1486,7 @@ multiclass VOP3P_Real_dpp<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
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: VOP3P_DPP16<op, !cast<VOP_DPP_Pseudo>(backing_ps_name #"_dpp"),
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Gen.Subtarget> {
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let AsmString = asmName #ps.Pfl.AsmVOP3DPP16;
1489-
let DecoderNamespace = "DPP"#Gen.DecoderNamespace;
1489+
let DecoderNamespace = Gen.DecoderNamespace;
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let AssemblerPredicate = Gen.AssemblerPredicate;
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}
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}
@@ -1496,7 +1496,7 @@ multiclass VOP3P_Real_dpp8<GFXGen Gen, bits<7> op, string backing_ps_name = NAME
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defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
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def _dpp8#Gen.Suffix : VOP3P_DPP8_Base<op, ps> {
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let AsmString = asmName #ps.Pfl.AsmVOP3DPP8;
1499-
let DecoderNamespace = "DPP8"#Gen.DecoderNamespace;
1499+
let DecoderNamespace = Gen.DecoderNamespace;
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let AssemblerPredicate = Gen.AssemblerPredicate;
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}
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}
@@ -1613,7 +1613,7 @@ multiclass VOP3P_Real_MFMA_gfx940_aliases<string NameFrom, string NameTo, string
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multiclass VOP3P_Real_MFMA_gfx940<bits<7> op, string Name = !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic,
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VOP3_Pseudo PS_ACD = !cast<VOP3_Pseudo>(NAME # "_e64"),
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VOP3_Pseudo PS_VCD = !cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64")> {
1616-
let SubtargetPredicate = isGFX940Plus,
1616+
let AssemblerPredicate = isGFX940Plus,
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DecoderNamespace = "GFX940",
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AsmString = Name # PS_ACD.AsmOperands, Constraints = "" in {
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def _gfx940_acd : VOP3P_Real<PS_ACD, SIEncodingFamily.GFX940>,

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