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Sean Fertile
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[PPC] cleanup of mayLoad/mayStore flags and memory operands.
1) Explicitly sets mayLoad/mayStore property in the tablegen files on load/store instructions. 2) Updated the flags on a number of intrinsics indicating that they write memory. 3) Added SDNPMemOperand flags for some target dependent SDNodes so that they propagate their memory operand Review: https://reviews.llvm.org/D28818 llvm-svn: 293200
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-44
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7 files changed

+46
-44
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‎llvm/include/llvm/IR/IntrinsicsPowerPC.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -203,19 +203,19 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
203203
// source address with a single pointer.
204204
def int_ppc_altivec_stvx :
205205
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
206-
[IntrArgMemOnly]>;
206+
[IntrWriteMem, IntrArgMemOnly]>;
207207
def int_ppc_altivec_stvxl :
208208
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
209-
[IntrArgMemOnly]>;
209+
[IntrWriteMem, IntrArgMemOnly]>;
210210
def int_ppc_altivec_stvebx :
211211
Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty],
212-
[IntrArgMemOnly]>;
212+
[IntrWriteMem, IntrArgMemOnly]>;
213213
def int_ppc_altivec_stvehx :
214214
Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty],
215-
[IntrArgMemOnly]>;
215+
[IntrWriteMem, IntrArgMemOnly]>;
216216
def int_ppc_altivec_stvewx :
217217
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
218-
[IntrArgMemOnly]>;
218+
[IntrWriteMem, IntrArgMemOnly]>;
219219

220220
// Comparisons setting a vector.
221221
def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">,
@@ -749,20 +749,20 @@ def int_ppc_vsx_lxvll :
749749
IntrArgMemOnly]>;
750750
def int_ppc_vsx_stxvl :
751751
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
752-
[IntrArgMemOnly]>;
752+
[IntrWriteMem, IntrArgMemOnly]>;
753753
def int_ppc_vsx_stxvll :
754754
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
755-
[IntrArgMemOnly]>;
755+
[IntrWriteMem, IntrArgMemOnly]>;
756756

757757
// Vector store.
758-
def int_ppc_vsx_stxvw4x :
759-
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
760-
def int_ppc_vsx_stxvd2x :
761-
Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
762-
def int_ppc_vsx_stxvw4x_be :
763-
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
764-
def int_ppc_vsx_stxvd2x_be :
765-
Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
758+
def int_ppc_vsx_stxvw4x : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
759+
[IntrWriteMem, IntrArgMemOnly]>;
760+
def int_ppc_vsx_stxvd2x : Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty],
761+
[IntrWriteMem, IntrArgMemOnly]>;
762+
def int_ppc_vsx_stxvw4x_be : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
763+
[IntrWriteMem, IntrArgMemOnly]>;
764+
def int_ppc_vsx_stxvd2x_be : Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty],
765+
[IntrWriteMem, IntrArgMemOnly]>;
766766
// Vector and scalar maximum.
767767
def int_ppc_vsx_xvmaxdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvmaxdp">;
768768
def int_ppc_vsx_xvmaxsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvmaxsp">;
@@ -953,7 +953,7 @@ class PowerPC_QPX_LoadPerm_Intrinsic<string GCCIntSuffix>
953953
class PowerPC_QPX_Store_Intrinsic<string GCCIntSuffix>
954954
: PowerPC_QPX_Intrinsic<GCCIntSuffix,
955955
[], [llvm_v4f64_ty, llvm_ptr_ty],
956-
[IntrArgMemOnly]>;
956+
[IntrWriteMem, IntrArgMemOnly]>;
957957

958958
//===----------------------------------------------------------------------===//
959959
// PowerPC QPX Intrinsic Definitions.

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2964,7 +2964,11 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
29642964
SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
29652965
SDValue Chain = LD->getChain();
29662966
SDValue Ops[] = { Base, Offset, Chain };
2967-
CurDAG->SelectNodeTo(N, PPC::LXVDSX, N->getValueType(0), Ops);
2967+
SDNode *NewN = CurDAG->SelectNodeTo(N, PPC::LXVDSX,
2968+
N->getValueType(0), Ops);
2969+
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2970+
MemOp[0] = LD->getMemOperand();
2971+
cast<MachineSDNode>(NewN)->setMemRefs(MemOp, MemOp + 1);
29682972
return;
29692973
}
29702974
}

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -253,11 +253,11 @@ def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
253253
Requires<[IsISA3_0]>;
254254
}
255255

256-
let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
256+
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
257257
def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
258258
"stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
259259

260-
let mayStore = 1, hasSideEffects = 0 in
260+
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
261261
def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
262262
"stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64,
263263
Requires<[IsISA3_0]>;
@@ -1082,7 +1082,7 @@ def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
10821082
}
10831083

10841084
// Stores with Update (pre-inc).
1085-
let PPC970_Unit = 2, mayStore = 1 in {
1085+
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
10861086
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
10871087
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
10881088
"stbu $rS, $dst", IIC_LdStStoreUpd, []>,

‎llvm/lib/Target/PowerPC/PPCInstrAltivec.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -407,7 +407,7 @@ def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
407407
"mtvscr $vB", IIC_LdStLoad,
408408
[(int_ppc_altivec_mtvscr v4i32:$vB)]>;
409409

410-
let PPC970_Unit = 2 in { // Loads.
410+
let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads.
411411
def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
412412
"lvebx $vD, $src", IIC_LdStLoad,
413413
[(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
@@ -434,7 +434,7 @@ def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
434434
[(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
435435
PPC970_Unit_LSU;
436436

437-
let PPC970_Unit = 2 in { // Stores.
437+
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores.
438438
def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
439439
"stvebx $rS, $dst", IIC_LdStStore,
440440
[(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -114,9 +114,9 @@ def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
114114
def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
115115
[SDNPHasChain, SDNPMayStore]>;
116116
def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
117-
[SDNPHasChain, SDNPMayLoad]>;
117+
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
118118
def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
119-
[SDNPHasChain, SDNPMayLoad]>;
119+
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
120120
def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,
121121
[SDNPHasChain, SDNPMayLoad]>;
122122
def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,
@@ -243,7 +243,7 @@ def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
243243
[SDNPHasChain, SDNPOptInGlue]>;
244244

245245
def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
246-
[SDNPHasChain, SDNPMayLoad]>;
246+
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
247247
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
248248
[SDNPHasChain, SDNPMayStore]>;
249249

@@ -1642,7 +1642,7 @@ let usesCustomInserter = 1 in {
16421642
}
16431643

16441644
// Instructions to support atomic operations
1645-
let mayLoad = 1, hasSideEffects = 0 in {
1645+
let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
16461646
def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
16471647
"lbarx $rD, $src", IIC_LdStLWARX, []>,
16481648
Requires<[HasPartwordAtomics]>;
@@ -1675,7 +1675,7 @@ def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
16751675
Requires<[IsISA3_0]>;
16761676
}
16771677

1678-
let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1678+
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
16791679
def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
16801680
"stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
16811681
isDOT, Requires<[HasPartwordAtomics]>;
@@ -1688,7 +1688,7 @@ def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
16881688
"stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
16891689
}
16901690

1691-
let mayStore = 1, hasSideEffects = 0 in
1691+
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
16921692
def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
16931693
"stwat $rS, $rA, $FC", IIC_LdStStore>,
16941694
Requires<[IsISA3_0]>;
@@ -1734,7 +1734,7 @@ def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
17341734

17351735

17361736
// Unindexed (r+i) Loads with Update (preinc).
1737-
let mayLoad = 1, hasSideEffects = 0 in {
1737+
let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
17381738
def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
17391739
"lbzu $rD, $addr", IIC_LdStLoadUpd,
17401740
[]>, RegConstraint<"$addr.reg = $ea_result">,
@@ -1807,7 +1807,7 @@ def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
18071807

18081808
// Indexed (r+r) Loads.
18091809
//
1810-
let PPC970_Unit = 2 in {
1810+
let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
18111811
def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
18121812
"lbzx $rD, $src", IIC_LdStLoad,
18131813
[(set i32:$rD, (zextloadi8 xaddr:$src))]>;
@@ -1821,8 +1821,6 @@ def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
18211821
def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
18221822
"lwzx $rD, $src", IIC_LdStLoad,
18231823
[(set i32:$rD, (load xaddr:$src))]>;
1824-
1825-
18261824
def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
18271825
"lhbrx $rD, $src", IIC_LdStLoad,
18281826
[(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
@@ -1854,7 +1852,7 @@ def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
18541852
//
18551853

18561854
// Unindexed (r+i) Stores.
1857-
let PPC970_Unit = 2 in {
1855+
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
18581856
def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
18591857
"stb $rS, $src", IIC_LdStStore,
18601858
[(truncstorei8 i32:$rS, iaddr:$src)]>;
@@ -1873,7 +1871,7 @@ def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
18731871
}
18741872

18751873
// Unindexed (r+i) Stores with Update (preinc).
1876-
let PPC970_Unit = 2, mayStore = 1 in {
1874+
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
18771875
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
18781876
"stbu $rS, $dst", IIC_LdStStoreUpd, []>,
18791877
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
@@ -1942,7 +1940,7 @@ def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
19421940
}
19431941

19441942
// Indexed (r+r) Stores with Update (preinc).
1945-
let PPC970_Unit = 2, mayStore = 1 in {
1943+
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
19461944
def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
19471945
"stbux $rS, $dst", IIC_LdStStoreUpd, []>,
19481946
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ def SDTVecConv : SDTypeProfile<1, 2, [
6262
]>;
6363

6464
def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
65-
[SDNPHasChain, SDNPMayLoad]>;
65+
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
6666
def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
6767
[SDNPHasChain, SDNPMayStore]>;
6868
def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
@@ -117,7 +117,7 @@ let hasSideEffects = 0 in { // VSX instructions don't have side effects.
117117
let Uses = [RM] in {
118118

119119
// Load indexed instructions
120-
let mayLoad = 1 in {
120+
let mayLoad = 1, mayStore = 0 in {
121121
let CodeSize = 3 in
122122
def LXSDX : XX1Form<31, 588,
123123
(outs vsfrc:$XT), (ins memrr:$src),
@@ -142,7 +142,7 @@ let Uses = [RM] in {
142142
} // mayLoad
143143

144144
// Store indexed instructions
145-
let mayStore = 1 in {
145+
let mayStore = 1, mayLoad = 0 in {
146146
let CodeSize = 3 in
147147
def STXSDX : XX1Form<31, 716,
148148
(outs), (ins vsfrc:$XT, memrr:$dst),
@@ -1197,7 +1197,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
11971197
[(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
11981198

11991199
// VSX scalar loads introduced in ISA 2.07
1200-
let mayLoad = 1 in {
1200+
let mayLoad = 1, mayStore = 0 in {
12011201
let CodeSize = 3 in
12021202
def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src),
12031203
"lxsspx $XT, $src", IIC_LdStLFD,
@@ -1211,7 +1211,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
12111211
} // mayLoad
12121212

12131213
// VSX scalar stores introduced in ISA 2.07
1214-
let mayStore = 1 in {
1214+
let mayStore = 1, mayLoad = 0 in {
12151215
let CodeSize = 3 in
12161216
def STXSSPX : XX1Form<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
12171217
"stxsspx $XT, $dst", IIC_LdStSTFD,
@@ -2335,7 +2335,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
23352335

23362336
// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
23372337
// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
2338-
let mayLoad = 1 in {
2338+
let mayLoad = 1, mayStore = 0 in {
23392339
// Load Vector
23402340
def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src),
23412341
"lxv $XT, $src", IIC_LdStLFD, []>, UseVSXReg;
@@ -2383,7 +2383,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
23832383

23842384
// When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
23852385
// PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
2386-
let mayStore = 1 in {
2386+
let mayStore = 1, mayLoad = 0 in {
23872387
// Store Vector
23882388
def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst),
23892389
"stxv $XT, $dst", IIC_LdStSTFD, []>, UseVSXReg;

‎llvm/test/CodeGen/PowerPC/swaps-le-7.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,11 @@
1111
; CHECK-LABEL: @zg
1212
; CHECK: xxspltd
1313
; CHECK-NEXT: xxspltd
14-
; CHECK-NEXT: xxswapd
1514
; CHECK-NEXT: xvmuldp
1615
; CHECK-NEXT: xvmuldp
1716
; CHECK-NEXT: xvsubdp
1817
; CHECK-NEXT: xvadddp
18+
; CHECK-NEXT: xxswapd
1919
; CHECK-NEXT: xxpermdi
2020
; CHECK-NEXT: xvsubdp
2121
; CHECK-NEXT: xxswapd
@@ -52,4 +52,4 @@ L.JA291:
5252
ret void
5353
}
5454

55-
attributes #0 = { noinline }
55+
attributes #0 = { noinline }

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