Skip to content

Commit 3cbc9eb

Browse files
XinWang10XinWang10
committed
resolve comments
1 parent 90844e2 commit 3cbc9eb

File tree

7 files changed

+115
-14
lines changed

7 files changed

+115
-14
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1054,7 +1054,7 @@ inline int getMemoryOperandNo(uint64_t TSFlags) {
10541054
// Skip registers encoded in reg, VEX_VVVV, and I8IMM.
10551055
return 3;
10561056
case X86II::MRMSrcMemCC:
1057-
return 1 + HasVEX_4V;
1057+
return 1 + hasNewDataDest(TSFlags);
10581058
case X86II::MRMDestMem4VOp3CC:
10591059
// Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
10601060
// mask register.

‎llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1740,7 +1740,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
17401740
break;
17411741
}
17421742
case X86II::MRMSrcRegCC: {
1743-
if (IsND)
1743+
if (IsND) // Skip new data destination
17441744
++CurOp;
17451745
unsigned FirstOp = CurOp++;
17461746
unsigned SecondOp = CurOp++;
@@ -1803,7 +1803,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
18031803
break;
18041804
}
18051805
case X86II::MRMSrcMemCC: {
1806-
if (IsND)
1806+
if (IsND) // Skip new data destination
18071807
++CurOp;
18081808
unsigned RegOp = CurOp++;
18091809
unsigned FirstMemOp = CurOp;

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2637,12 +2637,9 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
26372637
WorkingMI = CloneIfNew(MI);
26382638
WorkingMI->setDesc(get(Opc));
26392639
break;
2640-
case X86::CMOV16rr:
2641-
case X86::CMOV32rr:
2642-
case X86::CMOV64rr:
2643-
case X86::CMOV16rr_ND:
2644-
case X86::CMOV32rr_ND:
2645-
case X86::CMOV64rr_ND: {
2640+
CASE_ND(CMOV16rr)
2641+
CASE_ND(CMOV32rr)
2642+
CASE_ND(CMOV64rr) {
26462643
WorkingMI = CloneIfNew(MI);
26472644
unsigned OpNo = MI.getDesc().getNumOperands() - 1;
26482645
X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
@@ -3151,8 +3148,9 @@ X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
31513148
}
31523149

31533150
X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
3154-
return X86::isCMOVCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
3155-
: X86::COND_INVALID;
3151+
return X86::isCMOVCC(MI.getOpcode()) || X86::isCFCMOVCC(MI.getOpcode())
3152+
? X86::getCondFromMI(MI)
3153+
: X86::COND_INVALID;
31563154
}
31573155

31583156
/// Return the inverse of the specified condition,

‎llvm/test/CodeGen/X86/apx/cfcmov.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2+
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+cf -verify-machineinstrs | FileCheck %s
23
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+cf -x86-cmov-converter=false -verify-machineinstrs | FileCheck %s
34

45
define i8 @cfcmov8rr(i8 %0) {

‎llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,18 @@
2929
call void @foo()
3030
ret void
3131
}
32+
33+
define void @test_cmov(i64 %a, i64 %b) {
34+
entry:
35+
call void @foo()
36+
ret void
37+
}
38+
39+
define void @test_cfcmov(i64 %a, i64 %b) {
40+
entry:
41+
call void @foo()
42+
ret void
43+
}
3244
...
3345
---
3446
name: test_adc
@@ -166,3 +178,93 @@ body: |
166178
RET 0
167179
168180
...
181+
---
182+
name: test_cmov
183+
# CHECK-LABEL: name: test_cmov
184+
liveins:
185+
- { reg: '$rdi', virtual-reg: '%0' }
186+
- { reg: '$rsi', virtual-reg: '%1' }
187+
body: |
188+
bb.0:
189+
liveins: $rdi, $rsi
190+
191+
%0:gr64 = COPY $rdi
192+
%1:gr64 = COPY $rsi
193+
CMP64rr %0, %1, implicit-def $eflags
194+
%2:gr64 = COPY $eflags
195+
; CHECK-NOT: COPY{{( killed)?}} $eflags
196+
; CHECK: %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
197+
; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
198+
; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
199+
; CHECK-NOT: COPY{{( killed)?}} $eflags
200+
201+
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
202+
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
203+
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
204+
205+
$eflags = COPY %2
206+
%3:gr64 = CMOV64rr_ND %0, %1, 7, implicit $eflags
207+
%4:gr64 = CMOV64rr_ND %0, %1, 2, implicit $eflags
208+
%5:gr64 = CMOV64rr_ND %0, %1, 4, implicit $eflags
209+
%6:gr64 = CMOV64rr_ND %0, %1, 5, implicit killed $eflags
210+
; CHECK-NOT: $eflags =
211+
; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
212+
; CHECK-NEXT: %3:gr64 = CMOV64rr_ND %0, %1, 5, implicit killed $eflags
213+
; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
214+
; CHECK-NEXT: %4:gr64 = CMOV64rr_ND %0, %1, 5, implicit killed $eflags
215+
; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
216+
; CHECK-NEXT: %5:gr64 = CMOV64rr_ND %0, %1, 5, implicit killed $eflags
217+
; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
218+
; CHECK-NEXT: %6:gr64 = CMOV64rr_ND %0, %1, 4, implicit killed $eflags
219+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %3
220+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %4
221+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
222+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %6
223+
224+
RET 0
225+
...
226+
---
227+
name: test_cfcmov
228+
# CHECK-LABEL: name: test_cfcmov
229+
liveins:
230+
- { reg: '$rdi', virtual-reg: '%0' }
231+
- { reg: '$rsi', virtual-reg: '%1' }
232+
body: |
233+
bb.0:
234+
liveins: $rdi, $rsi
235+
236+
%0:gr64 = COPY $rdi
237+
%1:gr64 = COPY $rsi
238+
CMP64rr %0, %1, implicit-def $eflags
239+
%2:gr64 = COPY $eflags
240+
; CHECK-NOT: COPY{{( killed)?}} $eflags
241+
; CHECK: %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
242+
; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
243+
; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
244+
; CHECK-NOT: COPY{{( killed)?}} $eflags
245+
246+
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
247+
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
248+
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
249+
250+
$eflags = COPY %2
251+
%3:gr64 = CFCMOV64rr %1, 7, implicit $eflags
252+
%4:gr64 = CFCMOV64rr %1, 2, implicit $eflags
253+
%5:gr64 = CFCMOV64rr_ND %0, %1, 4, implicit $eflags
254+
%6:gr64 = CFCMOV64rr_ND %0, %1, 5, implicit killed $eflags
255+
; CHECK-NOT: $eflags =
256+
; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
257+
; CHECK-NEXT: %3:gr64 = CFCMOV64rr %1, 5, implicit killed $eflags
258+
; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
259+
; CHECK-NEXT: %4:gr64 = CFCMOV64rr %1, 5, implicit killed $eflags
260+
; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
261+
; CHECK-NEXT: %5:gr64 = CFCMOV64rr_ND %0, %1, 5, implicit killed $eflags
262+
; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
263+
; CHECK-NEXT: %6:gr64 = CFCMOV64rr_ND %0, %1, 4, implicit killed $eflags
264+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %3
265+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %4
266+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
267+
MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %6
268+
269+
RET 0
270+
...

‎llvm/utils/TableGen/X86ManualFoldTables.def

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,7 @@ NOFOLD(MMX_MOVQ64rr_REV)
227227
NOFOLD(INSERTPSrr)
228228
NOFOLD(VINSERTPSZrr)
229229
NOFOLD(VINSERTPSrr)
230-
// CFCMOV instructions have different semantics between rr and rm.
230+
// Memory faults are suppressed for CFCMOV with memory operand.
231231
NOFOLD(CFCMOV16rr)
232232
NOFOLD(CFCMOV32rr)
233233
NOFOLD(CFCMOV64rr)

‎llvm/utils/TableGen/X86RecognizableInstr.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -888,8 +888,8 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
888888
case X86Local::PrefixByte:
889889
filter = std::make_unique<DumbFilter>();
890890
break;
891-
case X86Local::MRMDestRegCC:
892891
case X86Local::MRMDestReg:
892+
case X86Local::MRMDestRegCC:
893893
case X86Local::MRMSrcReg:
894894
case X86Local::MRMSrcReg4VOp3:
895895
case X86Local::MRMSrcRegOp4:
@@ -898,8 +898,8 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
898898
case X86Local::MRMXr:
899899
filter = std::make_unique<ModFilter>(true);
900900
break;
901-
case X86Local::MRMDestMemCC:
902901
case X86Local::MRMDestMem:
902+
case X86Local::MRMDestMemCC:
903903
case X86Local::MRMDestMem4VOp3CC:
904904
case X86Local::MRMDestMemFSIB:
905905
case X86Local::MRMSrcMem:

0 commit comments

Comments
 (0)