@@ -1344,11 +1344,13 @@ static unsigned getNumAllocatableRegsForConstraints(
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return RCI.getNumAllocatableRegs (ConstrainedRC);
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}
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- // / Return true if \p MI at \P Use reads a subset of the lanes of \p VirtReg.
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- static bool readsLaneSubset (const MachineRegisterInfo &MRI,
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- const MachineInstr *MI, const LiveInterval &VirtReg,
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- const TargetRegisterInfo *TRI, SlotIndex Use,
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- const TargetInstrInfo *TII) {
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+ // / Return true if \p MI at \P Use reads a strict subset of the lanes of \p
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+ // / VirtReg (not the whole register).
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+ static bool readsLaneStrictSubset (const MachineRegisterInfo &MRI,
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+ const MachineInstr *MI,
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+ const LiveInterval &VirtReg,
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+ const TargetRegisterInfo *TRI,
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+ const TargetInstrInfo *TII) {
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// Early check the common case. Beware of the semi-formed bundles SplitKit
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// creates by setting the bundle flag on copies without a matching BUNDLE.
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@@ -1384,7 +1386,7 @@ static bool readsLaneSubset(const MachineRegisterInfo &MRI,
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// If the live lanes aren't different from the lanes used by the instruction,
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// this doesn't help.
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- return MRI.getMaxLaneMaskForVReg (VirtReg.reg ()) != UseMask ;
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+ return UseMask != MRI.getMaxLaneMaskForVReg (VirtReg.reg ());
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}
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// / tryInstructionSplit - Split a live range around individual instructions.
@@ -1436,7 +1438,7 @@ unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
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TII, TRI, RegClassInfo)) ||
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// TODO: Handle split for subranges with subclass constraints?
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(!SplitSubClass && VirtReg.hasSubRanges () &&
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- !readsLaneSubset (*MRI, MI, VirtReg, TRI, Use. getBaseIndex () , TII))) {
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+ !readsLaneStrictSubset (*MRI, MI, VirtReg, TRI, TII))) {
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LLVM_DEBUG (dbgs () << " skip:\t " << Use << ' \t ' << *MI);
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continue ;
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}
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