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Remove unused parameter and rename
1 parent edbde4a commit 3cc60ca

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+9
-7
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+9
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llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1344,11 +1344,13 @@ static unsigned getNumAllocatableRegsForConstraints(
13441344
return RCI.getNumAllocatableRegs(ConstrainedRC);
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}
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1347-
/// Return true if \p MI at \P Use reads a subset of the lanes of \p VirtReg.
1348-
static bool readsLaneSubset(const MachineRegisterInfo &MRI,
1349-
const MachineInstr *MI, const LiveInterval &VirtReg,
1350-
const TargetRegisterInfo *TRI, SlotIndex Use,
1351-
const TargetInstrInfo *TII) {
1347+
/// Return true if \p MI at \P Use reads a strict subset of the lanes of \p
1348+
/// VirtReg (not the whole register).
1349+
static bool readsLaneStrictSubset(const MachineRegisterInfo &MRI,
1350+
const MachineInstr *MI,
1351+
const LiveInterval &VirtReg,
1352+
const TargetRegisterInfo *TRI,
1353+
const TargetInstrInfo *TII) {
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// Early check the common case. Beware of the semi-formed bundles SplitKit
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// creates by setting the bundle flag on copies without a matching BUNDLE.
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@@ -1384,7 +1386,7 @@ static bool readsLaneSubset(const MachineRegisterInfo &MRI,
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13851387
// If the live lanes aren't different from the lanes used by the instruction,
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// this doesn't help.
1387-
return MRI.getMaxLaneMaskForVReg(VirtReg.reg()) != UseMask;
1389+
return UseMask != MRI.getMaxLaneMaskForVReg(VirtReg.reg());
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}
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13901392
/// tryInstructionSplit - Split a live range around individual instructions.
@@ -1436,7 +1438,7 @@ unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
14361438
TII, TRI, RegClassInfo)) ||
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// TODO: Handle split for subranges with subclass constraints?
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(!SplitSubClass && VirtReg.hasSubRanges() &&
1439-
!readsLaneSubset(*MRI, MI, VirtReg, TRI, Use.getBaseIndex(), TII))) {
1441+
!readsLaneStrictSubset(*MRI, MI, VirtReg, TRI, TII))) {
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LLVM_DEBUG(dbgs() << " skip:\t" << Use << '\t' << *MI);
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continue;
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}

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