Skip to content

Commit 3cec93b

Browse files
anton-afanasyevanton-afanasyev
committed
[SLP][Test] Precommit test for PR40522
1 parent c0cd527 commit 3cec93b

File tree

1 file changed

+113
-0
lines changed

1 file changed

+113
-0
lines changed

‎llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll

Lines changed: 113 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,113 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2+
; RUN: opt -slp-vectorizer -instcombine -S -mtriple=x86_64-- -mcpu=corei7 < %s | FileCheck %s
3+
4+
define void @test1(float %a, float %b, float %c, float %d, i32* nocapture %p) {
5+
; CHECK-LABEL: @test1(
6+
; CHECK-NEXT: entry:
7+
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
8+
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[B:%.*]], i32 1
9+
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[C:%.*]], i32 2
10+
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D:%.*]], i32 3
11+
; CHECK-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
12+
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32* [[P:%.*]] to <4 x i32>*
13+
; CHECK-NEXT: store <4 x i32> [[TMP4]], <4 x i32>* [[TMP5]], align 4, !tbaa [[TBAA0:![0-9]+]]
14+
; CHECK-NEXT: ret void
15+
;
16+
entry:
17+
%conv = fptosi float %a to i32
18+
%conv1 = fptosi float %b to i32
19+
%conv3 = fptosi float %c to i32
20+
%conv5 = fptosi float %d to i32
21+
%incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
22+
store i32 %conv, i32* %p, align 4, !tbaa !2
23+
%incdec.ptr8 = getelementptr inbounds i32, i32* %p, i64 2
24+
store i32 %conv1, i32* %incdec.ptr, align 4, !tbaa !2
25+
%incdec.ptr10 = getelementptr inbounds i32, i32* %p, i64 3
26+
store i32 %conv3, i32* %incdec.ptr8, align 4, !tbaa !2
27+
store i32 %conv5, i32* %incdec.ptr10, align 4, !tbaa !2
28+
ret void
29+
}
30+
31+
define void @test1_vec(float %a, float %b, float %c, float %d, <4 x i32>* nocapture %p) {
32+
; CHECK-LABEL: @test1_vec(
33+
; CHECK-NEXT: entry:
34+
; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[A:%.*]] to i32
35+
; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i32> undef, i32 [[CONV]], i32 0
36+
; CHECK-NEXT: [[CONV1:%.*]] = fptosi float [[B:%.*]] to i32
37+
; CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x i32> [[VECINIT]], i32 [[CONV1]], i32 1
38+
; CHECK-NEXT: [[CONV3:%.*]] = fptosi float [[C:%.*]] to i32
39+
; CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <4 x i32> [[VECINIT2]], i32 [[CONV3]], i32 2
40+
; CHECK-NEXT: [[CONV5:%.*]] = fptosi float [[D:%.*]] to i32
41+
; CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <4 x i32> [[VECINIT4]], i32 [[CONV5]], i32 3
42+
; CHECK-NEXT: store <4 x i32> [[VECINIT6]], <4 x i32>* [[P:%.*]], align 16, !tbaa [[TBAA0]]
43+
; CHECK-NEXT: ret void
44+
;
45+
entry:
46+
%conv = fptosi float %a to i32
47+
%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
48+
%conv1 = fptosi float %b to i32
49+
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
50+
%conv3 = fptosi float %c to i32
51+
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
52+
%conv5 = fptosi float %d to i32
53+
%vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
54+
store <4 x i32> %vecinit6, <4 x i32>* %p, align 16, !tbaa !2
55+
ret void
56+
}
57+
58+
define void @test2(i32 %a, i32 %b, i32 %c, i32 %d, i32* nocapture %p) {
59+
; CHECK-LABEL: @test2(
60+
; CHECK-NEXT: entry:
61+
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i32 0
62+
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[B:%.*]], i32 1
63+
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[C:%.*]], i32 2
64+
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[D:%.*]], i32 3
65+
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], <i32 1, i32 1, i32 1, i32 1>
66+
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32* [[P:%.*]] to <4 x i32>*
67+
; CHECK-NEXT: store <4 x i32> [[TMP4]], <4 x i32>* [[TMP5]], align 4, !tbaa [[TBAA0]]
68+
; CHECK-NEXT: ret void
69+
;
70+
entry:
71+
%add = add nsw i32 %a, 1
72+
%add1 = add nsw i32 %b, 1
73+
%add3 = add nsw i32 %c, 1
74+
%add5 = add nsw i32 %d, 1
75+
%incdec.ptr = getelementptr inbounds i32, i32* %p, i64 1
76+
store i32 %add, i32* %p, align 4, !tbaa !2
77+
%incdec.ptr8 = getelementptr inbounds i32, i32* %p, i64 2
78+
store i32 %add1, i32* %incdec.ptr, align 4, !tbaa !2
79+
%incdec.ptr10 = getelementptr inbounds i32, i32* %p, i64 3
80+
store i32 %add3, i32* %incdec.ptr8, align 4, !tbaa !2
81+
store i32 %add5, i32* %incdec.ptr10, align 4, !tbaa !2
82+
ret void
83+
}
84+
85+
define void @test2_vec(i32 %0, i32 %1, i32 %2, i32 %3, <4 x i32>* nocapture %4) {
86+
; CHECK-LABEL: @test2_vec(
87+
; CHECK-NEXT: [[TMP6:%.*]] = add nsw i32 [[TMP0:%.*]], 1
88+
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> undef, i32 [[TMP6]], i32 0
89+
; CHECK-NEXT: [[TMP8:%.*]] = add nsw i32 [[TMP1:%.*]], 1
90+
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP8]], i32 1
91+
; CHECK-NEXT: [[TMP10:%.*]] = add nsw i32 [[TMP2:%.*]], 1
92+
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP10]], i32 2
93+
; CHECK-NEXT: [[TMP12:%.*]] = add nsw i32 [[TMP3:%.*]], 1
94+
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP12]], i32 3
95+
; CHECK-NEXT: store <4 x i32> [[TMP13]], <4 x i32>* [[TMP4:%.*]], align 16, !tbaa [[TBAA0]]
96+
; CHECK-NEXT: ret void
97+
;
98+
%6 = add nsw i32 %0, 1
99+
%7 = insertelement <4 x i32> undef, i32 %6, i32 0
100+
%8 = add nsw i32 %1, 1
101+
%9 = insertelement <4 x i32> %7, i32 %8, i32 1
102+
%10 = add nsw i32 %2, 1
103+
%11 = insertelement <4 x i32> %9, i32 %10, i32 2
104+
%12 = add nsw i32 %3, 1
105+
%13 = insertelement <4 x i32> %11, i32 %12, i32 3
106+
store <4 x i32> %13, <4 x i32>* %4, align 16, !tbaa !2
107+
ret void
108+
}
109+
110+
!2 = !{!3, !3, i64 0}
111+
!3 = !{!"int", !4, i64 0}
112+
!4 = !{!"omnipotent char", !5, i64 0}
113+
!5 = !{!"Simple C++ TBAA"}

0 commit comments

Comments
 (0)