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Jinsong Ji
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[PowerPC][NFC] Rename ANDI(S)o8 to ANDI(S)8o
Summary: This is found during https://reviews.llvm.org/D70758 All the other record forms are having suffix o at the end. ANDIo8 and ANDISo8 are the only two that put o before 8. This patch rename them to be consistent with others. Reviewers: #powerpc, hfinkel, nemanjai, lei, steven.zhang, echristo, jhibbits, joerg Reviewed By: jhibbits Subscribers: wuzish, hiraditya, kbarton, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70928
1 parent 6dad5e4 commit 3d41a58

13 files changed

+44
-44
lines changed

‎llvm/lib/Target/PowerPC/P9InstrResources.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -130,7 +130,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
130130
(instregex "CMP(WI|LWI|W|LW)(8)?$"),
131131
(instregex "CMP(L)?D(I)?$"),
132132
(instregex "SUBF(I)?C(8)?(O)?$"),
133-
(instregex "ANDI(S)?o(8)?$"),
133+
(instregex "ANDI(S)?(8)?(o)?$"),
134134
(instregex "ADDC(8)?(O)?$"),
135135
(instregex "ADDIC(8)?(o)?$"),
136136
(instregex "ADD(8|4)(O)?(o)?$"),

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2181,12 +2181,12 @@ class BitPermutationSelector {
21812181

21822182
SDValue ANDIVal, ANDISVal;
21832183
if (ANDIMask != 0)
2184-
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2184+
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64,
21852185
ExtendToInt64(VRot, dl),
21862186
getI32Imm(ANDIMask, dl)),
21872187
0);
21882188
if (ANDISMask != 0)
2189-
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2189+
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64,
21902190
ExtendToInt64(VRot, dl),
21912191
getI32Imm(ANDISMask, dl)),
21922192
0);
@@ -2330,10 +2330,10 @@ class BitPermutationSelector {
23302330

23312331
SDValue ANDIVal, ANDISVal;
23322332
if (ANDIMask != 0)
2333-
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
2333+
ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64,
23342334
ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0);
23352335
if (ANDISMask != 0)
2336-
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
2336+
ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64,
23372337
ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0);
23382338

23392339
if (!ANDIVal)
@@ -2623,7 +2623,7 @@ SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) {
26232623
assert((NewOpc != -1 || !IsBitwiseNegate) &&
26242624
"No record form available for AND8/OR8/XOR8?");
26252625
WideOp =
2626-
SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
2626+
SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDI8o : NewOpc, dl,
26272627
MVT::i64, MVT::Glue, LHS, RHS), 0);
26282628
}
26292629

@@ -4790,7 +4790,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
47904790
assert((InVT == MVT::i64 || InVT == MVT::i32) &&
47914791
"Invalid input type for ANDIo_1_EQ_BIT");
47924792

4793-
unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
4793+
unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8o : PPC::ANDIo;
47944794
SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
47954795
N->getOperand(0),
47964796
CurDAG->getTargetConstant(1, dl, InVT)),
@@ -6304,8 +6304,8 @@ void PPCDAGToDAGISel::PeepholePPC64ZExt() {
63046304
case PPC::ORI: NewOpcode = PPC::ORI8; break;
63056305
case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
63066306
case PPC::AND: NewOpcode = PPC::AND8; break;
6307-
case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
6308-
case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
6307+
case PPC::ANDIo: NewOpcode = PPC::ANDI8o; break;
6308+
case PPC::ANDISo: NewOpcode = PPC::ANDIS8o; break;
63096309
}
63106310

63116311
// Note: During the replacement process, the nodes will be in an

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11624,7 +11624,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1162411624
MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) {
1162511625
unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
1162611626
MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
11627-
? PPC::ANDIo8
11627+
? PPC::ANDI8o
1162811628
: PPC::ANDIo;
1162911629
bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
1163011630
MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -474,11 +474,11 @@ defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
474474

475475
// Logical ops with immediate.
476476
let Defs = [CR0] in {
477-
def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
477+
def ANDI8o : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
478478
"andi. $dst, $src1, $src2", IIC_IntGeneral,
479479
[(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
480480
isDOT;
481-
def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
481+
def ANDIS8o : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
482482
"andis. $dst, $src1, $src2", IIC_IntGeneral,
483483
[(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
484484
isDOT;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1836,8 +1836,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
18361836

18371837
int NewOpC = -1;
18381838
int MIOpC = MI->getOpcode();
1839-
if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1840-
MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1839+
if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDI8o ||
1840+
MIOpC == PPC::ANDISo || MIOpC == PPC::ANDIS8o)
18411841
NewOpC = MIOpC;
18421842
else {
18431843
NewOpC = PPC::getRecordFormOpcode(MIOpC);
@@ -1945,15 +1945,15 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
19451945
Mask >>= MBInLoHWord ? 0 : 16;
19461946
NewOpC = MIOpC == PPC::RLWINM ?
19471947
(MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1948-
(MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1948+
(MBInLoHWord ? PPC::ANDI8o :PPC::ANDIS8o);
19491949
} else if (MRI->use_empty(GPRRes) && (ME == 31) &&
19501950
(ME - MB + 1 == SH) && (MB >= 16)) {
19511951
// If we are rotating by the exact number of bits as are in the mask
19521952
// and the mask is in the least significant bits of the register,
19531953
// that's just an andis. (as long as the GPR result has no uses).
19541954
Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
19551955
Mask >>= 16;
1956-
NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1956+
NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDIS8o;
19571957
}
19581958
// If we've set the mask, we can transform.
19591959
if (Mask != ~0LLU) {
@@ -1966,7 +1966,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
19661966
int64_t MB = MI->getOperand(3).getImm();
19671967
if (MB >= 48) {
19681968
uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1969-
NewOpC = PPC::ANDIo8;
1969+
NewOpC = PPC::ANDI8o;
19701970
MI->RemoveOperand(3);
19711971
MI->getOperand(2).setImm(Mask);
19721972
NumRcRotatesConvertedToRcAnd++;
@@ -2306,7 +2306,7 @@ void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
23062306

23072307
// Replace the instruction.
23082308
if (LII.SetCR) {
2309-
MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2309+
MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8o : PPC::ANDIo));
23102310
// Set the immediate.
23112311
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
23122312
.addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
@@ -3083,7 +3083,7 @@ bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
30833083
switch(Opc) {
30843084
default: llvm_unreachable("Unknown opcode");
30853085
case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
3086-
case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
3086+
case PPC::AND8o: III.ImmOpcode = PPC::ANDI8o; break;
30873087
case PPC::OR: III.ImmOpcode = PPC::ORI; break;
30883088
case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
30893089
case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
@@ -4067,8 +4067,8 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
40674067
case PPC::ORIS:
40684068
case PPC::XORI:
40694069
case PPC::XORIS:
4070-
case PPC::ANDIo8:
4071-
case PPC::ANDISo8:
4070+
case PPC::ANDI8o:
4071+
case PPC::ANDIS8o:
40724072
case PPC::ORI8:
40734073
case PPC::ORIS8:
40744074
case PPC::XORI8:

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1961,7 +1961,7 @@ def VectorExtractions {
19611961
- The order of elements after the move to GPR is reversed, so we invert
19621962
the bits of the index prior to truncating to the range 0-7
19631963
*/
1964-
dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDIo8 $Idx, 8)));
1964+
dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8o $Idx, 8)));
19651965
dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC));
19661966
dag BE_MV_VBYTE = (MFVSRD
19671967
(EXTRACT_SUBREG
@@ -1980,7 +1980,7 @@ def VectorExtractions {
19801980
the bits of the index prior to truncating to the range 0-3
19811981
*/
19821982
dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8,
1983-
(RLDICR (ANDIo8 $Idx, 4), 1, 62)));
1983+
(RLDICR (ANDI8o $Idx, 4), 1, 62)));
19841984
dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC));
19851985
dag BE_MV_VHALF = (MFVSRD
19861986
(EXTRACT_SUBREG
@@ -1998,7 +1998,7 @@ def VectorExtractions {
19981998
the bits of the index prior to truncating to the range 0-1
19991999
*/
20002000
dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2001-
(RLDICR (ANDIo8 $Idx, 2), 2, 61)));
2001+
(RLDICR (ANDI8o $Idx, 2), 2, 61)));
20022002
dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC));
20032003
dag BE_MV_VWORD = (MFVSRD
20042004
(EXTRACT_SUBREG
@@ -2014,7 +2014,7 @@ def VectorExtractions {
20142014
element indices.
20152015
*/
20162016
dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2017-
(RLDICR (ANDIo8 $Idx, 1), 3, 60)));
2017+
(RLDICR (ANDI8o $Idx, 1), 3, 60)));
20182018
dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC));
20192019
dag BE_VARIABLE_DWORD =
20202020
(MFVSRD (EXTRACT_SUBREG

‎llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -908,7 +908,7 @@ bool PPCMIPeephole::simplifyCode(void) {
908908
MI.RemoveOperand(4);
909909
MI.RemoveOperand(3);
910910
MI.getOperand(2).setImm(0);
911-
MI.setDesc(TII->get(Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
911+
MI.setDesc(TII->get(Is64Bit ? PPC::ANDI8o : PPC::ANDIo));
912912
}
913913
Simplified = true;
914914
NumRotatesCollapsed++;

‎llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1106,7 +1106,7 @@ body: |
11061106
%0 = COPY $x3
11071107
%2 = LI 88
11081108
%3 = SLDo %0, killed %2, implicit-def $cr0
1109-
; CHECK: ANDIo8 %0, 0, implicit-def $cr0
1109+
; CHECK: ANDI8o %0, 0, implicit-def $cr0
11101110
; CHECK-LATE: andi. 5, 3, 0
11111111
%4 = COPY killed $cr0
11121112
%5 = ISEL8 %1, %0, %4.sub_eq
@@ -1212,7 +1212,7 @@ body: |
12121212
%0 = COPY $x3
12131213
%2 = LI 64
12141214
%3 = SRDo %0, killed %2, implicit-def $cr0
1215-
; CHECK: ANDIo8 %0, 0, implicit-def $cr0
1215+
; CHECK: ANDI8o %0, 0, implicit-def $cr0
12161216
; CHECK-LATE: andi. 5, 3, 0
12171217
%4 = COPY killed $cr0
12181218
%5 = ISEL8 %1, %0, %4.sub_eq

‎llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1498,7 +1498,7 @@ body: |
14981498
%1 = LI8 321
14991499
%0 = COPY $x3
15001500
%2 = AND8o %1, %0, implicit-def $cr0
1501-
; CHECK: ANDIo8 %0, 321, implicit-def $cr0
1501+
; CHECK: ANDI8o %0, 321, implicit-def $cr0
15021502
; CHECK-LATE: andi. 5, 3, 321
15031503
%3 = COPY killed $cr0
15041504
%4 = ISEL8 %1, %0, %3.sub_eq
@@ -3928,7 +3928,7 @@ body: |
39283928
%1 = COPY $x4
39293929
%0 = LI8 -1
39303930
%2 = RLDICLo %0, 53, 48, implicit-def $cr0
3931-
; CHECK: ANDIo8 %0, 65535
3931+
; CHECK: ANDI8o %0, 65535
39323932
; CHECK-LATE: li 3, -1
39333933
; CHECK-LATE: andi. 3, 3, 65535
39343934
%3 = COPY killed $cr0
@@ -3983,7 +3983,7 @@ body: |
39833983
%0 = LI8 200
39843984
%2 = RLDICLo %0, 61, 3, implicit-def $cr0
39853985
; CHECK: LI8 25
3986-
; CHECK: ANDIo8 %0, 25
3986+
; CHECK: ANDI8o %0, 25
39873987
; CHECK-LATE-NOT: andi.
39883988
%3 = COPY killed $cr0
39893989
%4 = ISEL8 %1, %2, %3.sub_eq
@@ -4036,7 +4036,7 @@ body: |
40364036
%1 = COPY $x4
40374037
%0 = LI8 2
40384038
%2 = RLDICLo %0, 32, 32, implicit-def $cr0
4039-
; CHECK: ANDIo8 %0, 0
4039+
; CHECK: ANDI8o %0, 0
40404040
; CHECK-LATE: li 3, 2
40414041
; CHECK-LATE: andi. 3, 3, 0
40424042
%3 = COPY killed $cr0
@@ -4365,7 +4365,7 @@ body: |
43654365
%3 = LI -22
43664366
%4 = RLWINMo %3, 5, 24, 31, implicit-def $cr0
43674367
; CHECK: LI -22
4368-
; CHECK-NOT: ANDIo8 %3, 65514
4368+
; CHECK-NOT: ANDI8o %3, 65514
43694369
; CHECK-LATE-NOT: andi.
43704370
%5 = COPY killed $cr0
43714371
%6 = ISEL %2, %3, %5.sub_eq
@@ -4426,7 +4426,7 @@ body: |
44264426
%0 = COPY $x3
44274427
%2 = LI8 -18
44284428
%3 = RLWINM8o %2, 4, 20, 27, implicit-def $cr0
4429-
; CHECK: ANDIo8 %2, 3808
4429+
; CHECK: ANDI8o %2, 3808
44304430
; CHECK-LATE: li 3, -18
44314431
; CHECK-LATE: andi. 3, 3, 3808
44324432
%7 = COPY killed $cr0

‎llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ body: |
66
liveins: $x0, $x3
77
successors: %bb.1(0x40000000), %bb.2(0x40000000)
88
9-
dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
9+
dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
1010
$cr2lt = CROR $cr0gt, $cr0gt
1111
BCn killed renamable $cr2lt, %bb.2
1212
B %bb.1
@@ -26,7 +26,7 @@ body: |
2626

2727
# CHECK: body: |
2828
# CHECK: bb.0:
29-
# CHECK: dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
29+
# CHECK: dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
3030
# CHECK: $cr2lt = CROR $cr0gt, $cr0gt
3131
# CHECK: renamable $x3 = LIS8 4096
3232
# CHECK: MTLR8 $x0, implicit-def $lr8

‎llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,11 @@ define signext i32 @fn1(i32 %baz) {
77
%2 = zext i32 %1 to i64
88
%3 = shl i64 %2, 48
99
%4 = ashr exact i64 %3, 48
10-
; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead $cr0
10+
; CHECK: ANDI8o killed {{[^,]+}}, 65520, implicit-def dead $cr0
1111
; CHECK: CMPLDI
1212
; CHECK: BCC
1313

14-
; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def $cr0
14+
; CHECK: ANDI8o {{[^,]+}}, 65520, implicit-def $cr0
1515
; CHECK: COPY $cr0
1616
; CHECK: BCC
1717
%5 = icmp eq i64 %4, 0

‎llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,14 @@ body: |
1414
; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x5
1515
; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x4
1616
; CHECK: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
17-
; CHECK: [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0
17+
; CHECK: [[ANDI8o_:%[0-9]+]]:g8rc = ANDI8o [[COPY1]], 1, implicit-def $cr0
1818
; CHECK: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
1919
; CHECK: BCn killed [[COPY4]], %bb.2
2020
; CHECK: B %bb.1
2121
; CHECK: bb.1:
2222
; CHECK: liveins: $x3
2323
; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
24-
; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
24+
; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8o_]], 2, 61
2525
; CHECK: $x3 = COPY [[RLDICR]]
2626
; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
2727
; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
@@ -41,7 +41,7 @@ body: |
4141
%3:g8rc = COPY $x5
4242
%2:g8rc = COPY $x4
4343
%1:g8rc_and_g8rc_nox0 = COPY $x3
44-
%11:g8rc = ANDIo8 %3, 1, implicit-def $cr0
44+
%11:g8rc = ANDI8o %3, 1, implicit-def $cr0
4545
%6:crbitrc = COPY $cr0gt
4646
BCn killed %6, %bb.2
4747
B %bb.1

‎llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ body: |
297297
%0:g8rc = LI8 -11
298298
%2:g8rc_and_g8rc_nox0 = RLDICLo %0, 2, 49, implicit-def $cr0
299299
; CHECK: LI8 32727
300-
; CHECK: ANDIo8 %0, 32727
300+
; CHECK: ANDI8o %0, 32727
301301
; CHECK-LATE-NOT: andi.
302302
; CHECK-LATE: rldicl.
303303
%3:crrc = COPY killed $cr0
@@ -351,7 +351,7 @@ body: |
351351
%0:g8rc_and_g8rc_nox0 = LI8 1
352352
%2:g8rc = RLDICLo %0, 32, 33, implicit-def $cr0
353353
; CHECK: LI8 1
354-
; CHECK: ANDIo8 %0, 0
354+
; CHECK: ANDI8o %0, 0
355355
; CHECK-LATE: li [[IMM:[0-9]+]], 1
356356
; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
357357
%3:crrc = COPY killed $cr0
@@ -405,7 +405,7 @@ body: |
405405
%0:g8rc_and_g8rc_nox0 = LI8 -11
406406
%2:g8rc = RLDICLo %0, 2, 49, implicit-def $cr0
407407
; CHECK: LI8 -11
408-
; CHECK: ANDIo8 %0, 65525
408+
; CHECK: ANDI8o %0, 65525
409409
; CHECK-LATE-NOT: andi.
410410
; CHECK-LATE: rldicl.
411411
%3:crrc = COPY killed $cr0

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