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davemgreendavemgreen
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[AArch64][Arm] Add nested double reduction tests. NFC
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‎llvm/test/CodeGen/AArch64/double_reduct.ll

Lines changed: 365 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -284,6 +284,371 @@ define i32 @smax_i32(<8 x i32> %a, <4 x i32> %b) {
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ret i32 %r
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}
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define float @nested_fadd_f32(<4 x float> %a, <4 x float> %b, float %c, float %d) {
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; CHECK-LABEL: nested_fadd_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: faddp v1.4s, v1.4s, v1.4s
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; CHECK-NEXT: faddp v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: faddp s1, v1.2s
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: fadd s1, s1, s3
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: ret
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%r1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)
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%a1 = fadd fast float %r1, %c
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%r2 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %b)
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%a2 = fadd fast float %r2, %d
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%r = fadd fast float %a1, %a2
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ret float %r
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}
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define float @nested_fadd_f32_slow(<4 x float> %a, <4 x float> %b, float %c, float %d) {
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; CHECK-LABEL: nested_fadd_f32_slow:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov s4, v1.s[2]
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; CHECK-NEXT: mov s5, v0.s[2]
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; CHECK-NEXT: faddp s6, v0.2s
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; CHECK-NEXT: faddp s7, v1.2s
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; CHECK-NEXT: mov s1, v1.s[3]
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; CHECK-NEXT: mov s0, v0.s[3]
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; CHECK-NEXT: fadd s5, s6, s5
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; CHECK-NEXT: fadd s4, s7, s4
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; CHECK-NEXT: fadd s0, s5, s0
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; CHECK-NEXT: fadd s1, s4, s1
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; CHECK-NEXT: fadd s0, s0, s2
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; CHECK-NEXT: fadd s1, s1, s3
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: ret
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%r1 = call float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)
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%a1 = fadd float %r1, %c
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%r2 = call float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %b)
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%a2 = fadd float %r2, %d
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%r = fadd float %a1, %a2
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ret float %r
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}
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define float @nested_mul_f32(<4 x float> %a, <4 x float> %b, float %c, float %d) {
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; CHECK-LABEL: nested_mul_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: ext v5.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: fmul v1.2s, v1.2s, v4.2s
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; CHECK-NEXT: fmul v0.2s, v0.2s, v5.2s
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; CHECK-NEXT: fmul s1, s1, v1.s[1]
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; CHECK-NEXT: fmul s0, s0, v0.s[1]
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; CHECK-NEXT: fmul s1, s1, s3
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; CHECK-NEXT: fmul s0, s0, s2
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: ret
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%r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)
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%a1 = fmul fast float %r1, %c
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%r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)
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%a2 = fmul fast float %r2, %d
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%r = fmul fast float %a1, %a2
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ret float %r
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}
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define i32 @nested_add_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_add_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: addv s1, v1.4s
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: add w9, w9, w0
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; CHECK-NEXT: add w8, w8, w1
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; CHECK-NEXT: add w0, w9, w8
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
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%a1 = add i32 %r1, %c
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%r2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b)
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%a2 = add i32 %r2, %d
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%r = add i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_add_c1_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_add_c1_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: addv s1, v1.4s
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: add w9, w0, w9
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; CHECK-NEXT: add w8, w8, w1
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; CHECK-NEXT: add w0, w9, w8
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
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%a1 = add i32 %c, %r1
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%r2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b)
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%a2 = add i32 %r2, %d
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%r = add i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_add_c2_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_add_c2_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: addv s1, v1.4s
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: add w9, w9, w0
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; CHECK-NEXT: add w8, w1, w8
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; CHECK-NEXT: add w0, w9, w8
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
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%a1 = add i32 %r1, %c
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%r2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b)
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%a2 = add i32 %d, %r2
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%r = add i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_add_manyreduct_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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; CHECK-LABEL: nested_add_manyreduct_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
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%r3 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %c)
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%a1 = add i32 %r1, %r3
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%r2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b)
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%r4 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %d)
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%a2 = add i32 %r2, %r4
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%r = add i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_mul_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_mul_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: mul v0.2s, v0.2s, v3.2s
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; CHECK-NEXT: mul v1.2s, v1.2s, v2.2s
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: fmov w10, s0
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; CHECK-NEXT: mov w9, v1.s[1]
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; CHECK-NEXT: mul w8, w10, w8
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; CHECK-NEXT: fmov w10, s1
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; CHECK-NEXT: mul w9, w10, w9
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; CHECK-NEXT: mul w8, w8, w0
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; CHECK-NEXT: mul w9, w9, w1
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; CHECK-NEXT: mul w0, w8, w9
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)
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%a1 = mul i32 %r1, %c
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%r2 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %b)
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%a2 = mul i32 %r2, %d
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%r = mul i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_and_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_and_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: and v0.8b, v0.8b, v3.8b
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; CHECK-NEXT: fmov x8, d1
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: lsr x10, x9, #32
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; CHECK-NEXT: lsr x11, x8, #32
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; CHECK-NEXT: and w9, w9, w0
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; CHECK-NEXT: and w8, w8, w1
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; CHECK-NEXT: and w9, w9, w10
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; CHECK-NEXT: and w8, w8, w11
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
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%a1 = and i32 %r1, %c
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%r2 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %b)
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%a2 = and i32 %r2, %d
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%r = and i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_or_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_or_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: orr v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: orr v0.8b, v0.8b, v3.8b
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; CHECK-NEXT: fmov x8, d1
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: lsr x10, x9, #32
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; CHECK-NEXT: lsr x11, x8, #32
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; CHECK-NEXT: orr w9, w9, w0
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; CHECK-NEXT: orr w8, w8, w1
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; CHECK-NEXT: orr w9, w9, w10
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; CHECK-NEXT: orr w8, w8, w11
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; CHECK-NEXT: orr w0, w9, w8
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
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%a1 = or i32 %r1, %c
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%r2 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %b)
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%a2 = or i32 %r2, %d
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%r = or i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_xor_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_xor_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: eor v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: eor v0.8b, v0.8b, v3.8b
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; CHECK-NEXT: fmov x8, d1
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: lsr x10, x9, #32
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; CHECK-NEXT: lsr x11, x8, #32
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; CHECK-NEXT: eor w9, w9, w0
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; CHECK-NEXT: eor w8, w8, w1
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; CHECK-NEXT: eor w9, w9, w10
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; CHECK-NEXT: eor w8, w8, w11
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; CHECK-NEXT: eor w0, w9, w8
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)
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%a1 = xor i32 %r1, %c
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%r2 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %b)
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%a2 = xor i32 %r2, %d
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%r = xor i32 %a1, %a2
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ret i32 %r
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}
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define i32 @nested_smin_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_smin_i32:
531+
; CHECK: // %bb.0:
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; CHECK-NEXT: sminv s0, v0.4s
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; CHECK-NEXT: sminv s1, v1.4s
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: cmp w9, w0
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; CHECK-NEXT: csel w9, w9, w0, lt
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; CHECK-NEXT: cmp w8, w1
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; CHECK-NEXT: csel w8, w8, w1, lt
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; CHECK-NEXT: cmp w9, w8
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; CHECK-NEXT: csel w0, w9, w8, lt
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a)
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%a1 = call i32 @llvm.smin.i32(i32 %r1, i32 %c)
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%r2 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %b)
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%a2 = call i32 @llvm.smin.i32(i32 %r2, i32 %d)
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%r = call i32 @llvm.smin.i32(i32 %a1, i32 %a2)
548+
ret i32 %r
549+
}
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define i32 @nested_smax_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
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; CHECK-LABEL: nested_smax_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smaxv s0, v0.4s
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; CHECK-NEXT: smaxv s1, v1.4s
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: cmp w9, w0
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; CHECK-NEXT: csel w9, w9, w0, gt
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; CHECK-NEXT: cmp w8, w1
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; CHECK-NEXT: csel w8, w8, w1, gt
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; CHECK-NEXT: cmp w9, w8
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; CHECK-NEXT: csel w0, w9, w8, gt
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a)
566+
%a1 = call i32 @llvm.smax.i32(i32 %r1, i32 %c)
567+
%r2 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %b)
568+
%a2 = call i32 @llvm.smax.i32(i32 %r2, i32 %d)
569+
%r = call i32 @llvm.smax.i32(i32 %a1, i32 %a2)
570+
ret i32 %r
571+
}
572+
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define i32 @nested_umin_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
574+
; CHECK-LABEL: nested_umin_i32:
575+
; CHECK: // %bb.0:
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; CHECK-NEXT: uminv s0, v0.4s
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; CHECK-NEXT: uminv s1, v1.4s
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; CHECK-NEXT: fmov w9, s0
579+
; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: cmp w9, w0
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; CHECK-NEXT: csel w9, w9, w0, lo
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; CHECK-NEXT: cmp w8, w1
583+
; CHECK-NEXT: csel w8, w8, w1, lo
584+
; CHECK-NEXT: cmp w9, w8
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; CHECK-NEXT: csel w0, w9, w8, lo
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a)
588+
%a1 = call i32 @llvm.umin.i32(i32 %r1, i32 %c)
589+
%r2 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %b)
590+
%a2 = call i32 @llvm.umin.i32(i32 %r2, i32 %d)
591+
%r = call i32 @llvm.umin.i32(i32 %a1, i32 %a2)
592+
ret i32 %r
593+
}
594+
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define i32 @nested_umax_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
596+
; CHECK-LABEL: nested_umax_i32:
597+
; CHECK: // %bb.0:
598+
; CHECK-NEXT: umaxv s0, v0.4s
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; CHECK-NEXT: umaxv s1, v1.4s
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: cmp w9, w0
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; CHECK-NEXT: csel w9, w9, w0, hi
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; CHECK-NEXT: cmp w8, w1
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; CHECK-NEXT: csel w8, w8, w1, hi
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; CHECK-NEXT: cmp w9, w8
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; CHECK-NEXT: csel w0, w9, w8, hi
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; CHECK-NEXT: ret
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%r1 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a)
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%a1 = call i32 @llvm.umax.i32(i32 %r1, i32 %c)
611+
%r2 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %b)
612+
%a2 = call i32 @llvm.umax.i32(i32 %r2, i32 %d)
613+
%r = call i32 @llvm.umax.i32(i32 %a1, i32 %a2)
614+
ret i32 %r
615+
}
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define float @nested_fmin_float(<4 x float> %a, <4 x float> %b, float %c, float %d) {
618+
; CHECK-LABEL: nested_fmin_float:
619+
; CHECK: // %bb.0:
620+
; CHECK-NEXT: fminnmv s1, v1.4s
621+
; CHECK-NEXT: fminnmv s0, v0.4s
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; CHECK-NEXT: fminnm s1, s1, s3
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; CHECK-NEXT: fminnm s0, s0, s2
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; CHECK-NEXT: fminnm s0, s0, s1
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; CHECK-NEXT: ret
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%r1 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
627+
%a1 = call float @llvm.minnum.f32(float %r1, float %c)
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%r2 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %b)
629+
%a2 = call float @llvm.minnum.f32(float %r2, float %d)
630+
%r = call float @llvm.minnum.f32(float %a1, float %a2)
631+
ret float %r
632+
}
633+
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define float @nested_fmax_float(<4 x float> %a, <4 x float> %b, float %c, float %d) {
635+
; CHECK-LABEL: nested_fmax_float:
636+
; CHECK: // %bb.0:
637+
; CHECK-NEXT: fmaxnmv s1, v1.4s
638+
; CHECK-NEXT: fmaxnmv s0, v0.4s
639+
; CHECK-NEXT: fmaxnm s1, s1, s3
640+
; CHECK-NEXT: fmaxnm s0, s0, s2
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; CHECK-NEXT: fmaxnm s0, s0, s1
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; CHECK-NEXT: ret
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%r1 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
644+
%a1 = call float @llvm.maxnum.f32(float %r1, float %c)
645+
%r2 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %b)
646+
%a2 = call float @llvm.maxnum.f32(float %r2, float %d)
647+
%r = call float @llvm.maxnum.f32(float %a1, float %a2)
648+
ret float %r
649+
}
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declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>)
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declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
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declare float @llvm.vector.reduce.fmul.f32.v8f32(float, <8 x float>)

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