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[InstCombine] Add a test for splitting scalable structs. NFC
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‎llvm/test/Transforms/InstCombine/scalable-vector-struct.ll

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@@ -28,3 +28,122 @@ define void @store(ptr %x, <vscale x 1 x i32> %y, <vscale x 1 x i32> %z) {
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store %struct.test %b, ptr %x
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ret void
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}
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define {<vscale x 16 x i8>, <vscale x 16 x i8>} @split_load(ptr %p) nounwind {
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; CHECK-LABEL: define { <vscale x 16 x i8>, <vscale x 16 x i8> } @split_load
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; CHECK-SAME: (ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[R:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[P]], align 16
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; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8> } [[R]]
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;
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entry:
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%r = load {<vscale x 16 x i8>, <vscale x 16 x i8>}, ptr %p
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ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %r
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}
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define {<vscale x 16 x i8>} @split_load_one(ptr %p) nounwind {
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; CHECK-LABEL: define { <vscale x 16 x i8> } @split_load_one
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; CHECK-SAME: (ptr [[P:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[R_UNPACK:%.*]] = load <vscale x 16 x i8>, ptr [[P]], align 16
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; CHECK-NEXT: [[R1:%.*]] = insertvalue { <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[R_UNPACK]], 0
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; CHECK-NEXT: ret { <vscale x 16 x i8> } [[R1]]
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;
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entry:
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%r = load {<vscale x 16 x i8>}, ptr %p
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ret {<vscale x 16 x i8>} %r
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}
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define void @split_store({<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p) nounwind {
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; CHECK-LABEL: define void @split_store
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; CHECK-SAME: ({ <vscale x 4 x i32>, <vscale x 4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], ptr [[P]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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store {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p
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ret void
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}
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define void @split_store_one({<vscale x 4 x i32>} %x, ptr %p) nounwind {
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; CHECK-LABEL: define void @split_store_one
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; CHECK-SAME: ({ <vscale x 4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { <vscale x 4 x i32> } [[X]], 0
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; CHECK-NEXT: store <vscale x 4 x i32> [[TMP0]], ptr [[P]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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store {<vscale x 4 x i32>} %x, ptr %p
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ret void
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}
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define {<16 x i8>, <16 x i8>} @check_v16i8_v4i32({<4 x i32>, <4 x i32>} %x, ptr %p) nounwind {
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; CHECK-LABEL: define { <16 x i8>, <16 x i8> } @check_v16i8_v4i32
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; CHECK-SAME: ({ <4 x i32>, <4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X_ELT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[X]], 0
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; CHECK-NEXT: store <4 x i32> [[X_ELT]], ptr [[P]], align 16
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; CHECK-NEXT: [[P_REPACK1:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 16
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; CHECK-NEXT: [[X_ELT2:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[X]], 1
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; CHECK-NEXT: store <4 x i32> [[X_ELT2]], ptr [[P_REPACK1]], align 16
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; CHECK-NEXT: [[R_UNPACK_CAST:%.*]] = bitcast <4 x i32> [[X_ELT]] to <16 x i8>
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; CHECK-NEXT: [[TMP0:%.*]] = insertvalue { <16 x i8>, <16 x i8> } poison, <16 x i8> [[R_UNPACK_CAST]], 0
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; CHECK-NEXT: [[R_UNPACK4_CAST:%.*]] = bitcast <4 x i32> [[X_ELT2]] to <16 x i8>
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; CHECK-NEXT: [[R5:%.*]] = insertvalue { <16 x i8>, <16 x i8> } [[TMP0]], <16 x i8> [[R_UNPACK4_CAST]], 1
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; CHECK-NEXT: ret { <16 x i8>, <16 x i8> } [[R5]]
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;
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entry:
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store {<4 x i32>, <4 x i32>} %x, ptr %p
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%r = load {<16 x i8>, <16 x i8>}, ptr %p
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ret {<16 x i8>, <16 x i8>} %r
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}
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define {<vscale x 16 x i8>, <vscale x 16 x i8>} @check_nxv16i8_nxv4i32({<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p) nounwind {
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; CHECK-LABEL: define { <vscale x 16 x i8>, <vscale x 16 x i8> } @check_nxv16i8_nxv4i32
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; CHECK-SAME: ({ <vscale x 4 x i32>, <vscale x 4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], ptr [[P]], align 16
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; CHECK-NEXT: [[R:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[P]], align 16
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; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8> } [[R]]
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;
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entry:
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store {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p
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%r = load {<vscale x 16 x i8>, <vscale x 16 x i8>}, ptr %p
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ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %r
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}
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define {<vscale x 16 x i8>, <vscale x 16 x i8>} @alloca_nxv16i8_nxv4i32({<vscale x 4 x i32>, <vscale x 4 x i32>} %x) nounwind {
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; CHECK-LABEL: define { <vscale x 16 x i8>, <vscale x 16 x i8> } @alloca_nxv16i8_nxv4i32
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; CHECK-SAME: ({ <vscale x 4 x i32>, <vscale x 4 x i32> } [[X:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[P:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
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; CHECK-NEXT: store { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], ptr [[P]], align 16
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; CHECK-NEXT: [[R:%.*]] = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr [[P]], align 16
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; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8> } [[R]]
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;
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entry:
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%p = alloca {<vscale x 4 x i32>, <vscale x 4 x i32>}
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store {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p
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%r = load {<vscale x 16 x i8>, <vscale x 16 x i8>}, ptr %p
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ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %r
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}
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define { <16 x i8>, <32 x i8> } @differenttypes({ <4 x i32>, <8 x i32> } %a, ptr %p) {
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; CHECK-LABEL: define { <16 x i8>, <32 x i8> } @differenttypes
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; CHECK-SAME: ({ <4 x i32>, <8 x i32> } [[A:%.*]], ptr [[P:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr nonnull [[P]])
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; CHECK-NEXT: store { <4 x i32>, <8 x i32> } [[A]], ptr [[P]], align 16
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; CHECK-NEXT: [[TMP0:%.*]] = load { <16 x i8>, <32 x i8> }, ptr [[P]], align 16
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; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr nonnull [[P]])
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; CHECK-NEXT: ret { <16 x i8>, <32 x i8> } [[TMP0]]
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;
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entry:
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call void @llvm.lifetime.start.p0(i64 -1, ptr nonnull %p) #5
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store { <4 x i32>, <8 x i32> } %a, ptr %p, align 16
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%2 = load { <16 x i8>, <32 x i8> }, ptr %p, align 16
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call void @llvm.lifetime.end.p0(i64 -1, ptr nonnull %p) #5
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ret { <16 x i8>, <32 x i8> } %2
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}

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