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[RISCV] Add MC layer support for Zicfiss. (#66043)
The patch adds the instructions in Zicfiss extension. Zicfiss extension is to support shadow stack for control flow integrity. This patch is based on version [0.3.1]. [0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
1 parent fe2e677 commit 3dc0638

16 files changed

+340
-11
lines changed

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@
118118
// CHECK-NOT: __riscv_zfa {{.*$}}
119119
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
120120
// CHECK-NOT: __riscv_zicfilp {{.*$}}
121+
// CHECK-NOT: __riscv_zicfiss {{.*$}}
121122
// CHECK-NOT: __riscv_zicond {{.*$}}
122123
// CHECK-NOT: __riscv_zimop {{.*$}}
123124
// CHECK-NOT: __riscv_zcmop {{.*$}}
@@ -1287,3 +1288,11 @@
12871288
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
12881289
// RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST
12891290
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
1291+
1292+
// RUN: %clang -target riscv32 -menable-experimental-extensions \
1293+
// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \
1294+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
1295+
// RUN: %clang -target riscv64 -menable-experimental-extensions \
1296+
// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \
1297+
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
1298+
// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,7 @@ The primary goal of experimental support is to assist in the process of ratifica
212212
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
213213
LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.
214214

215-
``experimental-zicfilp``
215+
``experimental-zicfilp``, ``experimental-zicfiss``
216216
LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__.
217217

218218
``experimental-zicond``

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
195195
{"zfbfmin", RISCVExtensionVersion{0, 8}},
196196

197197
{"zicfilp", RISCVExtensionVersion{0, 4}},
198+
{"zicfiss", RISCVExtensionVersion{0, 4}},
199+
198200
{"zicond", RISCVExtensionVersion{1, 0}},
199201

200202
{"zimop", RISCVExtensionVersion{0, 1}},
@@ -1021,6 +1023,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"};
10211023
static const char *ImpliedExtsZhinx[] = {"zhinxmin"};
10221024
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
10231025
static const char *ImpliedExtsZicntr[] = {"zicsr"};
1026+
static const char *ImpliedExtsZicfiss[] = {"zicsr", "zimop"};
10241027
static const char *ImpliedExtsZihpm[] = {"zicsr"};
10251028
static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
10261029
static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
@@ -1093,6 +1096,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
10931096
{{"zfinx"}, {ImpliedExtsZfinx}},
10941097
{{"zhinx"}, {ImpliedExtsZhinx}},
10951098
{{"zhinxmin"}, {ImpliedExtsZhinxmin}},
1099+
{{"zicfiss"}, {ImpliedExtsZicfiss}},
10961100
{{"zicntr"}, {ImpliedExtsZicntr}},
10971101
{{"zihpm"}, {ImpliedExtsZihpm}},
10981102
{{"zk"}, {ImpliedExtsZk}},

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
7474
return MCDisassembler::Success;
7575
}
7676

77+
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
78+
uint64_t Address,
79+
const MCDisassembler *Decoder) {
80+
MCRegister Reg = RISCV::X0 + RegNo;
81+
if (Reg != RISCV::X1 && Reg != RISCV::X5)
82+
return MCDisassembler::Fail;
83+
84+
Inst.addOperand(MCOperand::createReg(Reg));
85+
return MCDisassembler::Success;
86+
}
87+
7788
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
7889
uint64_t Address,
7990
const MCDisassembler *Decoder) {
@@ -359,6 +370,10 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
359370
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
360371
uint64_t Address, const void *Decoder);
361372

373+
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
374+
uint64_t Address,
375+
const MCDisassembler *Decoder);
376+
362377
#include "RISCVGenDisassemblerTables.inc"
363378

364379
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
@@ -373,6 +388,16 @@ static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
373388
return MCDisassembler::Success;
374389
}
375390

391+
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
392+
uint64_t Address,
393+
const MCDisassembler *Decoder) {
394+
uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
395+
DecodeStatus Result = DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
396+
(void)Result;
397+
assert(Result == MCDisassembler::Success && "Invalid register");
398+
return MCDisassembler::Success;
399+
}
400+
376401
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
377402
uint64_t Address,
378403
const MCDisassembler *Decoder) {
@@ -596,6 +621,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
596621
TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
597622
DecoderTableRISCV32Only_16,
598623
"RISCV32Only_16 table (16-bit Instruction)");
624+
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16,
625+
"RVZicfiss table (Shadow Stack)");
599626
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
600627
"Zcmt table (16-bit Table Jump Instructions)");
601628
TRY_TO_DECODE_FEATURE(

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -700,6 +700,15 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
700700
AssemblerPredicate<(all_of FeatureStdExtZcmop),
701701
"'Zcmop' (Compressed May-Be-Operations)">;
702702

703+
def FeatureStdExtZicfiss
704+
: SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true",
705+
"'Zicfiss' (Shadow stack)",
706+
[FeatureStdExtZicsr, FeatureStdExtZimop]>;
707+
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
708+
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
709+
"'Zicfiss' (Shadow stack)">;
710+
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
711+
703712
def FeatureStdExtSmaia
704713
: SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
705714
"'Smaia' (Smaia encompasses all added CSRs and all "

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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Original file line numberDiff line numberDiff line change
@@ -2111,16 +2111,17 @@ include "RISCVInstrInfoZk.td"
21112111
include "RISCVInstrInfoV.td"
21122112
include "RISCVInstrInfoZvk.td"
21132113

2114-
// Integer
2115-
include "RISCVInstrInfoZimop.td"
2116-
include "RISCVInstrInfoZicbo.td"
2117-
include "RISCVInstrInfoZicond.td"
2118-
21192114
// Compressed
21202115
include "RISCVInstrInfoC.td"
21212116
include "RISCVInstrInfoZc.td"
21222117
include "RISCVInstrInfoZcmop.td"
21232118

2119+
// Integer
2120+
include "RISCVInstrInfoZimop.td"
2121+
include "RISCVInstrInfoZicbo.td"
2122+
include "RISCVInstrInfoZicond.td"
2123+
include "RISCVInstrInfoZicfiss.td"
2124+
21242125
//===----------------------------------------------------------------------===//
21252126
// Vendor extensions
21262127
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,13 @@ class CMOPInst<bits<3> imm3, string opcodestr>
2222
let Inst{12-11} = 0;
2323
}
2424

25-
foreach i = 0...7 in {
26-
let Predicates = [HasStdExtZcmop] in {
27-
defvar n = !add(!mul(i, 2), 1);
28-
def CMOP # n : CMOPInst<i, "cmop." # n>, Sched<[]>;
29-
} // Predicates = [HasStdExtZcmop]
25+
// CMOP1, CMOP5 is used by Zicfiss.
26+
let Predicates = [HasStdExtZcmop, NoHasStdExtZicfiss] in {
27+
def CMOP1 : CMOPInst<0, "cmop.1">, Sched<[]>;
28+
def CMOP5 : CMOPInst<2, "cmop.5">, Sched<[]>;
29+
}
30+
31+
foreach n = [3, 7, 9, 11, 13, 15] in {
32+
let Predicates = [HasStdExtZcmop] in
33+
def CMOP # n : CMOPInst<!srl(n, 1), "cmop." # n>, Sched<[]>;
3034
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td

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@@ -0,0 +1,72 @@
1+
//===------ RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen -*------===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
//===----------------------------------------------------------------------===//
10+
// Instruction class templates
11+
//===----------------------------------------------------------------------===//
12+
13+
class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :
14+
RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> {
15+
let Inst{15-13} = 0b011;
16+
let Inst{12} = 0;
17+
let Inst{11-7} = rs1val;
18+
let Inst{6-2} = 0b00000;
19+
let Inst{1-0} = 0b01;
20+
let DecoderMethod = "decodeCSSPushPopchk";
21+
}
22+
23+
//===----------------------------------------------------------------------===//
24+
// Instructions
25+
//===----------------------------------------------------------------------===//
26+
27+
let Predicates = [HasStdExtZicfiss] in {
28+
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
29+
def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",
30+
"$rs1"> {
31+
let rd = 0;
32+
let imm12 = 0b110011011100;
33+
} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
34+
35+
let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
36+
def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"> {
37+
let imm12 = 0b110011011100;
38+
let rs1 = 0b00000;
39+
}
40+
} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
41+
42+
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
43+
def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
44+
"sspush", "$rs2"> {
45+
let rd = 0b00000;
46+
let rs1 = 0b00000;
47+
}
48+
} // Predicates = [HasStdExtZicfiss]
49+
50+
let Predicates = [HasStdExtZicfiss, HasStdExtZcmop],
51+
DecoderNamespace = "Zicfiss" in {
52+
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
53+
def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;
54+
55+
let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
56+
def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
57+
} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]
58+
59+
let Predicates = [HasStdExtZicfiss] in
60+
defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
61+
62+
let Predicates = [HasStdExtZicfiss, IsRV64] in
63+
defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
64+
65+
//===----------------------------------------------------------------------===/
66+
// Compress Instruction tablegen backend.
67+
//===----------------------------------------------------------------------===//
68+
69+
let Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in {
70+
def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;
71+
def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;
72+
} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,9 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
127127
markSuperRegs(Reserved, RISCV::X27);
128128
}
129129

130+
// Shadow stack pointer.
131+
markSuperRegs(Reserved, RISCV::SSP);
132+
130133
assert(checkAllSuperRegsMarked(Reserved));
131134
return Reserved;
132135
}

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,8 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
137137
(sequence "X%u", 0, 4))>;
138138

139139
def GPRX0 : GPRRegisterClass<(add X0)>;
140+
def GPRX1 : GPRRegisterClass<(add X1)>;
141+
def GPRX5 : GPRRegisterClass<(add X5)>;
140142

141143
def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
142144

@@ -165,6 +167,8 @@ def SP : GPRRegisterClass<(add X2)>;
165167
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
166168
(sequence "X%u", 18, 23))>;
167169

170+
def GPRX1X5 : GPRRegisterClass<(add X1, X5)>;
171+
168172
// Floating point registers
169173
let RegAltNameIndices = [ABIRegAltName] in {
170174
def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
@@ -591,3 +595,6 @@ foreach m = LMULList in {
591595
// Special registers
592596
def FFLAGS : RISCVReg<0, "fflags">;
593597
def FRM : RISCVReg<0, "frm">;
598+
599+
// Shadow Stack register
600+
def SSP : RISCVReg<0, "ssp">;

‎llvm/test/MC/RISCV/attribute-arch.s

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Original file line numberDiff line numberDiff line change
@@ -309,5 +309,8 @@
309309
.attribute arch, "rv32i_zicfilp0p4"
310310
# CHECK: attribute 5, "rv32i2p1_zicfilp0p4"
311311

312+
.attribute arch, "rv32i_zicfiss0p4"
313+
# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop0p1"
314+
312315
.attribute arch, "rv64i_xsfvfwmaccqqq"
313316
# CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0"

‎llvm/test/MC/RISCV/compressed-zicfiss.s

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@@ -0,0 +1,53 @@
1+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+experimental-zcmop -riscv-no-aliases -show-encoding \
2+
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+experimental-zcmop < %s \
4+
# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+experimental-zcmop -M no-aliases -d -r - \
5+
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
6+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+experimental-zcmop -riscv-no-aliases -show-encoding \
7+
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
8+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+experimental-zcmop < %s \
9+
# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+experimental-zcmop -M no-aliases -d -r - \
10+
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
11+
#
12+
# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
13+
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
14+
15+
# CHECK-ASM-AND-OBJ: c.sspopchk t0
16+
# CHECK-ASM: encoding: [0x81,0x62]
17+
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
18+
sspopchk x5
19+
20+
# CHECK-ASM-AND-OBJ: c.sspopchk t0
21+
# CHECK-ASM: encoding: [0x81,0x62]
22+
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
23+
sspopchk t0
24+
25+
# CHECK-ASM-AND-OBJ: c.sspush ra
26+
# CHECK-ASM: encoding: [0x81,0x60]
27+
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
28+
sspush x1
29+
30+
# CHECK-ASM-AND-OBJ: c.sspush ra
31+
# CHECK-ASM: encoding: [0x81,0x60]
32+
# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack)
33+
sspush ra
34+
35+
# CHECK-ASM-AND-OBJ: c.sspush ra
36+
# CHECK-ASM: encoding: [0x81,0x60]
37+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
38+
c.sspush x1
39+
40+
# CHECK-ASM-AND-OBJ: c.sspush ra
41+
# CHECK-ASM: encoding: [0x81,0x60]
42+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
43+
c.sspush ra
44+
45+
# CHECK-ASM-AND-OBJ: c.sspopchk t0
46+
# CHECK-ASM: encoding: [0x81,0x62]
47+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
48+
c.sspopchk x5
49+
50+
# CHECK-ASM-AND-OBJ: c.sspopchk t0
51+
# CHECK-ASM: encoding: [0x81,0x62]
52+
# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack)
53+
c.sspopchk t0

‎llvm/test/MC/RISCV/rv32zicfiss-invalid.s

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
2+
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
3+
4+
# CHECK-ERR: error: invalid operand for instruction
5+
sspopchk a1
6+
7+
# CHECK-ERR: error: invalid operand for instruction
8+
c.sspush t0
9+
10+
# CHECK-ERR: error: invalid operand for instruction
11+
c.sspopchk ra
12+
13+
# CHECK-ERR: error: invalid operand for instruction
14+
sspush a0
15+
16+
# CHECK-ERR: error: invalid operand for instruction
17+
ssrdp zero

‎llvm/test/MC/RISCV/rv64zicfiss-invalid.s

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \
2+
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
3+
4+
# CHECK-ERR: error: invalid operand for instruction
5+
sspopchk a1
6+
7+
# CHECK-ERR: error: invalid operand for instruction
8+
c.sspush t0
9+
10+
# CHECK-ERR: error: invalid operand for instruction
11+
c.sspopchk ra
12+
13+
# CHECK-ERR: error: invalid operand for instruction
14+
sspush a0
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# CHECK-ERR: error: invalid operand for instruction
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ssrdp zero

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