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GlobalISel: Implement fewerElements for implicit_def
llvm-svn: 350697
1 parent bdbe5c7 commit 3dddb16

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4 files changed

+78
-4
lines changed

4 files changed

+78
-4
lines changed

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1172,6 +1172,32 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
11721172
switch (MI.getOpcode()) {
11731173
default:
11741174
return UnableToLegalize;
1175+
case TargetOpcode::G_IMPLICIT_DEF: {
1176+
SmallVector<unsigned, 2> DstRegs;
1177+
1178+
unsigned NarrowSize = NarrowTy.getSizeInBits();
1179+
unsigned DstReg = MI.getOperand(0).getReg();
1180+
unsigned Size = MRI.getType(DstReg).getSizeInBits();
1181+
int NumParts = Size / NarrowSize;
1182+
// FIXME: Don't know how to handle the situation where the small vectors
1183+
// aren't all the same size yet.
1184+
if (Size % NarrowSize != 0)
1185+
return UnableToLegalize;
1186+
1187+
for (int i = 0; i < NumParts; ++i) {
1188+
unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1189+
MIRBuilder.buildUndef(TmpReg);
1190+
DstRegs.push_back(TmpReg);
1191+
}
1192+
1193+
if (NarrowTy.isVector())
1194+
MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1195+
else
1196+
MIRBuilder.buildBuildVector(DstReg, DstRegs);
1197+
1198+
MI.eraseFromParent();
1199+
return Legalized;
1200+
}
11751201
case TargetOpcode::G_ADD: {
11761202
unsigned NarrowSize = NarrowTy.getSizeInBits();
11771203
unsigned DstReg = MI.getOperand(0).getReg();

llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -48,9 +48,21 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
4848
const LLT v2s64 = LLT::vector(2, 64);
4949

5050
getActionDefinitionsBuilder(G_IMPLICIT_DEF)
51-
.legalFor({p0, s1, s8, s16, s32, s64, v2s64})
52-
.clampScalar(0, s1, s64)
53-
.widenScalarToNextPow2(0, 8);
51+
.legalFor({p0, s1, s8, s16, s32, s64, v2s64})
52+
.clampScalar(0, s1, s64)
53+
.widenScalarToNextPow2(0, 8)
54+
.fewerElementsIf(
55+
[=](const LegalityQuery &Query) {
56+
return Query.Types[0].isVector() &&
57+
(Query.Types[0].getElementType() != s64 ||
58+
Query.Types[0].getNumElements() != 2);
59+
},
60+
[=](const LegalityQuery &Query) {
61+
LLT EltTy = Query.Types[0].getElementType();
62+
if (EltTy == s64)
63+
return std::make_pair(0, LLT::vector(2, 64));
64+
return std::make_pair(0, EltTy);
65+
});
5466

5567
getActionDefinitionsBuilder(G_PHI)
5668
.legalFor({p0, s16, s32, s64})

llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,3 +35,39 @@ body: |
3535
...
3636

3737
# FIXME: s2 not correctly handled
38+
39+
---
40+
name: test_implicit_def_v2s32
41+
body: |
42+
bb.0:
43+
44+
; CHECK-LABEL: name: test_implicit_def_v2s32
45+
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
46+
; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
47+
; CHECK: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
48+
; CHECK: [[DEF3:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
49+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF1]](s32), [[DEF2]](s32), [[DEF3]](s32)
50+
; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
51+
; CHECK: $x0 = COPY [[UV]](<2 x s32>)
52+
; CHECK: $x1 = COPY [[UV1]](<2 x s32>)
53+
%0:_(<4 x s32>) = G_IMPLICIT_DEF
54+
%1:_(<2 x s32> ), %2:_(<2 x s32>) = G_UNMERGE_VALUES %0
55+
$x0 = COPY %1
56+
$x1 = COPY %2
57+
...
58+
59+
---
60+
name: test_implicit_def_v4s64
61+
body: |
62+
bb.0:
63+
64+
; CHECK-LABEL: name: test_implicit_def_v4s64
65+
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
66+
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
67+
; CHECK: $q0 = COPY [[DEF]](<2 x s64>)
68+
; CHECK: $q1 = COPY [[DEF1]](<2 x s64>)
69+
%0:_(<4 x s64>) = G_IMPLICIT_DEF
70+
%1:_(<2 x s64> ), %2:_(<2 x s64>) = G_UNMERGE_VALUES %0
71+
$q0 = COPY %1
72+
$q1 = COPY %2
73+
...

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@
4646
# DEBUG: .. the first uncovered type index: 1, OK
4747
#
4848
# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index
49-
# DEBUG: .. the first uncovered type index: 1, OK
49+
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
5050
#
5151
# DEBUG-NEXT: G_PHI (opcode {{[0-9]+}}): 1 type index
5252
# DEBUG: .. the first uncovered type index: 1, OK

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