[RISCV] Precommit test coverage for insert_vector_elt with exact VLEN

Author: preames

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

@@ -564,3 +564,133 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
   store <8 x i64> %d, ptr %x
   ret void
 }
+
+; The next batch of tests cover inserts into high LMUL vectors when the
+; exact VLEM is known.  FIXME: These can directly access the sub-registers
+
+define <16 x i32> @insertelt_c0_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c0_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e32, m1, tu, ma
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 0
+  ret <16 x i32> %v
+}
+
+define <16 x i32> @insertelt_c1_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c1_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
+; CHECK-NEXT:    vmv.s.x v12, a0
+; CHECK-NEXT:    vslideup.vi v8, v12, 1
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 1
+  ret <16 x i32> %v
+}
+
+define <16 x i32> @insertelt_c2_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c2_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, tu, ma
+; CHECK-NEXT:    vmv.s.x v12, a0
+; CHECK-NEXT:    vslideup.vi v8, v12, 2
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 2
+  ret <16 x i32> %v
+}
+
+define <16 x i32> @insertelt_c3_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c3_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT:    vmv.s.x v12, a0
+; CHECK-NEXT:    vslideup.vi v8, v12, 3
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 3
+  ret <16 x i32> %v
+}
+
+define <16 x i32> @insertelt_c12_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c12_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 13, e32, m4, tu, ma
+; CHECK-NEXT:    vmv.s.x v12, a0
+; CHECK-NEXT:    vslideup.vi v8, v12, 12
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 12
+  ret <16 x i32> %v
+}
+
+define <16 x i32> @insertelt_c13_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c13_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 14, e32, m4, tu, ma
+; CHECK-NEXT:    vmv.s.x v12, a0
+; CHECK-NEXT:    vslideup.vi v8, v12, 13
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 13
+  ret <16 x i32> %v
+}
+
+define <16 x i32> @insertelt_c14_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c14_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 15, e32, m4, tu, ma
+; CHECK-NEXT:    vmv.s.x v12, a0
+; CHECK-NEXT:    vslideup.vi v8, v12, 14
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 14
+  ret <16 x i32> %v
+}
+
+define <16 x i32> @insertelt_c15_v16xi32_exact(<16 x i32> %vin, i32 %a) vscale_range(2,2) {
+; CHECK-LABEL: insertelt_c15_v16xi32_exact:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT:    vmv.s.x v12, a0
+; CHECK-NEXT:    vslideup.vi v8, v12, 15
+; CHECK-NEXT:    ret
+  %v = insertelement <16 x i32> %vin, i32 %a, i32 15
+  ret <16 x i32> %v
+}
+
+define <8 x i64> @insertelt_c4_v8xi64_exact(<8 x i64> %vin, i64 %a) vscale_range(2,2) {
+; RV32-LABEL: insertelt_c4_v8xi64_exact:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetivli zero, 2, e32, m4, ta, ma
+; RV32-NEXT:    vslide1down.vx v12, v8, a0
+; RV32-NEXT:    vslide1down.vx v12, v12, a1
+; RV32-NEXT:    vsetivli zero, 5, e64, m4, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v12, 4
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: insertelt_c4_v8xi64_exact:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetivli zero, 5, e64, m4, tu, ma
+; RV64-NEXT:    vmv.s.x v12, a0
+; RV64-NEXT:    vslideup.vi v8, v12, 4
+; RV64-NEXT:    ret
+  %v = insertelement <8 x i64> %vin, i64 %a, i32 4
+  ret <8 x i64> %v
+}
+
+define <8 x i64> @insertelt_c5_v8xi64_exact(<8 x i64> %vin, i64 %a) vscale_range(2,2) {
+; RV32-LABEL: insertelt_c5_v8xi64_exact:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetivli zero, 2, e32, m4, ta, ma
+; RV32-NEXT:    vslide1down.vx v12, v8, a0
+; RV32-NEXT:    vslide1down.vx v12, v12, a1
+; RV32-NEXT:    vsetivli zero, 6, e64, m4, tu, ma
+; RV32-NEXT:    vslideup.vi v8, v12, 5
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: insertelt_c5_v8xi64_exact:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vsetivli zero, 6, e64, m4, tu, ma
+; RV64-NEXT:    vmv.s.x v12, a0
+; RV64-NEXT:    vslideup.vi v8, v12, 5
+; RV64-NEXT:    ret
+  %v = insertelement <8 x i64> %vin, i64 %a, i32 5
+  ret <8 x i64> %v
+}