[AMDGPU][MC][GFX9] Corrected SMEM decoding

Corrected SMEM decoding when IMM=0 and OFFSET>127

Fixed bug 49819 (https://bugs.llvm.org/show_bug.cgi?id=49819)

Differential Revision: https://reviews.llvm.org/D99804

Author: dpreobra

llvm/lib/Target/AMDGPU/SMInstructions.td

@@ -515,7 +515,8 @@ class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
 
   // VI supports 20-bit unsigned offsets while GFX9+ supports 21-bit signed.
   // Offset value is corrected accordingly when offset is encoded/decoded.
-  let Inst{52-32} = !if(ps.has_offset, offset{20-0}, ?);
+  let Inst{38-32} = !if(ps.has_offset, offset{6-0}, ?);
+  let Inst{52-39} = !if(ps.has_offset, !if(imm, offset{20-7}, ?), ?);
 }
 
 multiclass SM_Real_Loads_vi<bits<8> op, string ps,

llvm/test/MC/Disassembler/AMDGPU/smem_gfx9.txt

@@ -291,3 +291,16 @@
 
 # GFX9: s_atc_probe_buffer 1, s[8:11], -0x1 ; encoding: [0x44,0x00,0x9e,0xc0,0xff,0xff,0x1f,0x00]
 0x44,0x00,0x9e,0xc0,0xff,0xff,0x1f,0x00
+
+#===------------------------------------------------------------------------===#
+# Decoding of OFFSET>127 with IMM=0
+#===------------------------------------------------------------------------===#
+
+# GFX9: s_atomic_or s5, s[2:3], s15             ; encoding: [0x41,0x01,0x24,0xc2,0x0f,0x00,0x00,0x00]
+0x41,0x01,0x24,0xc2,0x8f,0x00,0x00,0x00
+
+# GFX9: s_atomic_or s5, s[2:3], exec_hi         ; encoding: [0x41,0x01,0x24,0xc2,0x7f,0x00,0x00,0x00]
+0x41,0x01,0x24,0xc2,0xff,0xff,0x00,0x00
+
+# GFX9: s_atomic_add_x2 s[34:35], exec, s11 glc ; encoding: [0xbf,0x08,0x89,0xc2,0x0b,0x00,0x00,0x00]
+0xbf,0x08,0x89,0xc2,0x0b,0x00,0x00,0x00