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vitalybukavitalybuka
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[NFC][InstCombine][SROA][Asan] Precommit test affected by #100773
Some optimizations need to be undone with sanitizers by #100773. Pull Request: #100844
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‎llvm/test/Transforms/InstCombine/load.ll

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,16 @@ define i32 @test5(i1 %C) {
5656
ret i32 %Z
5757
}
5858

59+
define i32 @test5_asan(i1 %C) sanitize_address {
60+
; CHECK-LABEL: @test5_asan(
61+
; CHECK-NEXT: [[Z:%.*]] = select i1 [[C:%.*]], i32 42, i32 47
62+
; CHECK-NEXT: ret i32 [[Z]]
63+
;
64+
%Y = select i1 %C, ptr @X, ptr @X2 ; <ptr> [#uses=1]
65+
%Z = load i32, ptr %Y ; <i32> [#uses=1]
66+
ret i32 %Z
67+
}
68+
5969
define i32 @load_gep_null_inbounds(i64 %X) {
6070
; CHECK-LABEL: @load_gep_null_inbounds(
6171
; CHECK-NEXT: store i1 true, ptr poison, align 1

‎llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,3 +25,27 @@ define void @PR35618(ptr %st1, ptr %st2) {
2525
ret void
2626
}
2727

28+
define void @PR35618_asan(ptr %st1, ptr %st2) sanitize_address {
29+
; CHECK-LABEL: @PR35618_asan(
30+
; CHECK-NEXT: [[Y1:%.*]] = alloca double, align 8
31+
; CHECK-NEXT: [[Z1:%.*]] = alloca double, align 8
32+
; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1]], align 8
33+
; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1]], align 8
34+
; CHECK-NEXT: [[TMP:%.*]] = fcmp olt double [[LD1]], [[LD2]]
35+
; CHECK-NEXT: [[TMP12_V:%.*]] = select i1 [[TMP]], double [[LD1]], double [[LD2]]
36+
; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST1:%.*]], align 8
37+
; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST2:%.*]], align 8
38+
; CHECK-NEXT: ret void
39+
;
40+
%y1 = alloca double
41+
%z1 = alloca double
42+
%ld1 = load double, ptr %y1
43+
%ld2 = load double, ptr %z1
44+
%tmp = fcmp olt double %ld1, %ld2
45+
%sel = select i1 %tmp, ptr %y1, ptr %z1
46+
%tmp12 = load i64, ptr %sel
47+
store i64 %tmp12, ptr %st1
48+
store i64 %tmp12, ptr %st2
49+
ret void
50+
}
51+

‎llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -427,6 +427,21 @@ entry:
427427
ret i8 %load
428428
}
429429

430+
define i8 @select_diff_addrspace_remove_alloca_asan(i1 %cond, ptr %p) sanitize_address {
431+
; CHECK-LABEL: @select_diff_addrspace_remove_alloca_asan(
432+
; CHECK-NEXT: entry:
433+
; CHECK-NEXT: ret i8 0
434+
;
435+
entry:
436+
%alloca = alloca [32 x i8]
437+
call void @llvm.memcpy.p0.p1.i64(ptr %alloca, ptr addrspace(1) @g2, i64 32, i1 false)
438+
%gep = getelementptr inbounds [32 x i8], ptr %alloca, i32 0, i32 2
439+
%sel = select i1 %cond, ptr %alloca, ptr %gep
440+
%gep2 = getelementptr inbounds i8, ptr %sel, i64 4
441+
%load = load i8, ptr %gep2
442+
ret i8 %load
443+
}
444+
430445
declare i8 @readonly_callee(ptr readonly nocapture)
431446

432447
; FIXME: This should be able to fold to call i8 @readonly_callee(ptr nonnull @g1)

‎llvm/test/Transforms/InstCombine/select-load.ll

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,104 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2+
; RUN: opt -passes=instcombine -S < %s | FileCheck %s
3+
4+
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
5+
target triple = "x86_64-grtev4-linux-gnu"
6+
7+
define i32 @test_plain(i1 %f) {
8+
; CHECK-LABEL: @test_plain(
9+
; CHECK-NEXT: entry:
10+
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 8
11+
; CHECK-NEXT: [[B:%.*]] = alloca i32, align 8
12+
; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]], align 8
13+
; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]], align 8
14+
; CHECK-NEXT: [[L:%.*]] = select i1 [[F:%.*]], i32 [[A_VAL]], i32 [[B_VAL]]
15+
; CHECK-NEXT: ret i32 [[L]]
16+
;
17+
entry:
18+
%a = alloca i32, align 8
19+
%b = alloca i32, align 8
20+
%sel = select i1 %f, ptr %a, ptr %b
21+
%l = load i32, ptr %sel, align 8
22+
ret i32 %l
23+
}
24+
25+
; Don't speculate as the condition may control which memory is valid from
26+
; sanitizer perspective.
27+
define i32 @test_asan(i1 %f) sanitize_address {
28+
; CHECK-LABEL: @test_asan(
29+
; CHECK-NEXT: entry:
30+
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 8
31+
; CHECK-NEXT: [[B:%.*]] = alloca i32, align 8
32+
; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]], align 8
33+
; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]], align 8
34+
; CHECK-NEXT: [[L:%.*]] = select i1 [[F:%.*]], i32 [[A_VAL]], i32 [[B_VAL]]
35+
; CHECK-NEXT: ret i32 [[L]]
36+
;
37+
entry:
38+
%a = alloca i32, align 8
39+
%b = alloca i32, align 8
40+
%sel = select i1 %f, ptr %a, ptr %b
41+
%l = load i32, ptr %sel, align 8
42+
ret i32 %l
43+
}
44+
45+
46+
; Don't speculate as the condition may control which memory is valid from
47+
; sanitizer perspective.
48+
define i32 @test_hwasan(i1 %f) sanitize_hwaddress {
49+
; CHECK-LABEL: @test_hwasan(
50+
; CHECK-NEXT: entry:
51+
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 8
52+
; CHECK-NEXT: [[B:%.*]] = alloca i32, align 8
53+
; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]], align 8
54+
; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]], align 8
55+
; CHECK-NEXT: [[L:%.*]] = select i1 [[F:%.*]], i32 [[A_VAL]], i32 [[B_VAL]]
56+
; CHECK-NEXT: ret i32 [[L]]
57+
;
58+
entry:
59+
%a = alloca i32, align 8
60+
%b = alloca i32, align 8
61+
%sel = select i1 %f, ptr %a, ptr %b
62+
%l = load i32, ptr %sel, align 8
63+
ret i32 %l
64+
}
65+
66+
; Don't speculate as the condition may control which memory is valid from
67+
; sanitizer perspective.
68+
define i32 @test_tsan(i1 %f) sanitize_thread {
69+
; CHECK-LABEL: @test_tsan(
70+
; CHECK-NEXT: entry:
71+
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 8
72+
; CHECK-NEXT: [[B:%.*]] = alloca i32, align 8
73+
; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]], align 8
74+
; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]], align 8
75+
; CHECK-NEXT: [[L:%.*]] = select i1 [[F:%.*]], i32 [[A_VAL]], i32 [[B_VAL]]
76+
; CHECK-NEXT: ret i32 [[L]]
77+
;
78+
entry:
79+
%a = alloca i32, align 8
80+
%b = alloca i32, align 8
81+
%sel = select i1 %f, ptr %a, ptr %b
82+
%l = load i32, ptr %sel, align 8
83+
ret i32 %l
84+
}
85+
86+
; Msan just propagates shadow, even if speculated load accesses uninitialized
87+
; value, instrumentation will select shadow of the desired value anyway.
88+
define i32 @test_msan(i1 %f) sanitize_memory {
89+
; CHECK-LABEL: @test_msan(
90+
; CHECK-NEXT: entry:
91+
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 8
92+
; CHECK-NEXT: [[B:%.*]] = alloca i32, align 8
93+
; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]], align 8
94+
; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]], align 8
95+
; CHECK-NEXT: [[L:%.*]] = select i1 [[F:%.*]], i32 [[A_VAL]], i32 [[B_VAL]]
96+
; CHECK-NEXT: ret i32 [[L]]
97+
;
98+
entry:
99+
%a = alloca i32, align 8
100+
%b = alloca i32, align 8
101+
%sel = select i1 %f, ptr %a, ptr %b
102+
%l = load i32, ptr %sel, align 8
103+
ret i32 %l
104+
}

‎llvm/test/Transforms/InstCombine/strnlen-2.ll

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,16 @@ define i64 @fold_strnlen_s3_s5_1(i1 %C) {
3838
ret i64 %len
3939
}
4040

41+
define i64 @fold_strnlen_s3_s5_1_asan(i1 %C) sanitize_address {
42+
; CHECK-LABEL: @fold_strnlen_s3_s5_1_asan(
43+
; CHECK-NEXT: ret i64 1
44+
;
45+
%ptr = select i1 %C, ptr @s3, ptr @s6
46+
47+
%len = call i64 @strnlen(ptr %ptr, i64 1)
48+
ret i64 %len
49+
}
50+
4151

4252
; Fold strnlen (C ? s3 : s5, 3) to 3.
4353

‎llvm/test/Transforms/SROA/phi-and-select.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -344,6 +344,27 @@ entry:
344344
ret i32 %loaded
345345
}
346346

347+
; We should not unconditionally load with sanitizers.
348+
define i32 @test9_asan(i32 %b, ptr %ptr) sanitize_address {
349+
; Same as @test8 but for a select rather than a PHI node.
350+
;
351+
; CHECK-LABEL: @test9_asan(
352+
; CHECK-NEXT: entry:
353+
; CHECK-NEXT: store i32 0, ptr [[PTR:%.*]], align 4
354+
; CHECK-NEXT: [[TEST:%.*]] = icmp ne i32 [[B:%.*]], 0
355+
; CHECK-NEXT: [[LOADED_SROA_SPECULATE_LOAD_FALSE:%.*]] = load i32, ptr [[PTR]], align 4
356+
; CHECK-NEXT: [[LOADED_SROA_SPECULATED:%.*]] = select i1 [[TEST]], i32 undef, i32 [[LOADED_SROA_SPECULATE_LOAD_FALSE]]
357+
; CHECK-NEXT: ret i32 [[LOADED_SROA_SPECULATED]]
358+
;
359+
entry:
360+
%f = alloca float
361+
store i32 0, ptr %ptr
362+
%test = icmp ne i32 %b, 0
363+
%select = select i1 %test, ptr %f, ptr %ptr
364+
%loaded = load i32, ptr %select, align 4
365+
ret i32 %loaded
366+
}
367+
347368
define float @test10(i32 %b, ptr %ptr) {
348369
; Don't try to promote allocas which are not elligible for it even after
349370
; rewriting due to the necessity of inserting bitcasts when speculating a PHI

‎llvm/test/Transforms/SROA/phi-with-duplicate-pred.ll

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,51 @@ cleanup7: ; preds = %cleanup
5252
ret void
5353
}
5454

55+
define void @f2_hwasan(i1 %c1) sanitize_hwaddress {
56+
; CHECK-LABEL: @f2_hwasan(
57+
; CHECK-NEXT: entry:
58+
; CHECK-NEXT: br i1 [[C1:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
59+
; CHECK: if.then:
60+
; CHECK-NEXT: br label [[CLEANUP:%.*]]
61+
; CHECK: cleanup:
62+
; CHECK-NEXT: [[G_0_SROA_SPECULATE_LOAD_CLEANUP:%.*]] = load i16, ptr @a, align 1
63+
; CHECK-NEXT: switch i32 2, label [[CLEANUP7:%.*]] [
64+
; CHECK-NEXT: i32 0, label [[LBL1:%.*]]
65+
; CHECK-NEXT: i32 2, label [[LBL1]]
66+
; CHECK-NEXT: ]
67+
; CHECK: if.else:
68+
; CHECK-NEXT: br label [[LBL1]]
69+
; CHECK: lbl1:
70+
; CHECK-NEXT: [[G_0_SROA_SPECULATED:%.*]] = phi i16 [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ undef, [[IF_ELSE]] ]
71+
; CHECK-NEXT: unreachable
72+
; CHECK: cleanup7:
73+
; CHECK-NEXT: ret void
74+
;
75+
entry:
76+
%e = alloca i16, align 1
77+
br i1 %c1, label %if.then, label %if.else
78+
79+
if.then: ; preds = %entry
80+
br label %cleanup
81+
82+
cleanup: ; preds = %if.then
83+
switch i32 2, label %cleanup7 [
84+
i32 0, label %lbl1
85+
i32 2, label %lbl1
86+
]
87+
88+
if.else: ; preds = %entry
89+
br label %lbl1
90+
91+
lbl1: ; preds = %if.else, %cleanup, %cleanup
92+
%g.0 = phi ptr [ @a, %cleanup ], [ @a, %cleanup ], [ %e, %if.else ]
93+
%0 = load i16, ptr %g.0, align 1
94+
unreachable
95+
96+
cleanup7: ; preds = %cleanup
97+
ret void
98+
}
99+
55100
define void @f3(i1 %c1) {
56101
; CHECK-LABEL: @f3(
57102
; CHECK-NEXT: entry:

‎llvm/test/Transforms/SROA/select-load.ll

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ entry:
3636
%st.args = type { i32, ptr }
3737

3838
; A bitcasted load and a direct load of select.
39-
define void @test_multiple_loads_select(i1 %cmp){
39+
define void @test_multiple_loads_select(i1 %cmp) {
4040
; CHECK-LABEL: @test_multiple_loads_select(
4141
; CHECK-NEXT: entry:
4242
; CHECK-NEXT: [[ADDR_I8_SROA_SPECULATED:%.*]] = select i1 [[CMP:%.*]], ptr undef, ptr undef
@@ -57,6 +57,28 @@ entry:
5757
ret void
5858
}
5959

60+
; Sanitizer will break optimization.
61+
define void @test_multiple_loads_select_asan(i1 %cmp) sanitize_address {
62+
; CHECK-LABEL: @test_multiple_loads_select_asan(
63+
; CHECK-NEXT: entry:
64+
; CHECK-NEXT: [[ADDR_I8_SROA_SPECULATED:%.*]] = select i1 [[CMP:%.*]], ptr undef, ptr undef
65+
; CHECK-NEXT: call void @foo_i8(ptr [[ADDR_I8_SROA_SPECULATED]])
66+
; CHECK-NEXT: [[ADDR_I32_SROA_SPECULATED:%.*]] = select i1 [[CMP]], ptr undef, ptr undef
67+
; CHECK-NEXT: call void @foo_i32(ptr [[ADDR_I32_SROA_SPECULATED]])
68+
; CHECK-NEXT: ret void
69+
;
70+
entry:
71+
%args = alloca [2 x %st.args], align 16
72+
%arr1 = getelementptr inbounds [2 x %st.args], ptr %args, i64 0, i64 1
73+
%sel = select i1 %cmp, ptr %arr1, ptr %args
74+
%addr = getelementptr inbounds %st.args, ptr %sel, i64 0, i32 1
75+
%addr.i8 = load ptr, ptr %addr, align 8
76+
call void @foo_i8(ptr %addr.i8)
77+
%addr.i32 = load ptr, ptr %addr, align 8
78+
call void @foo_i32 (ptr %addr.i32)
79+
ret void
80+
}
81+
6082
declare void @foo_i8(ptr)
6183
declare void @foo_i32(ptr)
6284

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