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[AArch64][GlobalISel] Pre-Commit Test for G_STORE v4s8
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‎llvm/test/CodeGen/AArch64/store.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; CHECK-GI: warning: Instruction selection used fallback path for store_v4i8
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; ===== Legal Scalars =====
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define void @store_i8(i8 %a, ptr %ptr){
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; CHECK-LABEL: store_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: strb w0, [x1]
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; CHECK-NEXT: ret
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store i8 %a, ptr %ptr
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ret void
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}
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define void @store_i16(i16 %a, ptr %ptr){
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; CHECK-LABEL: store_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: strh w0, [x1]
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; CHECK-NEXT: ret
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store i16 %a, ptr %ptr
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ret void
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}
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define void @store_i32(i32 %a, ptr %ptr){
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; CHECK-LABEL: store_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str w0, [x1]
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; CHECK-NEXT: ret
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store i32 %a, ptr %ptr
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ret void
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}
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define void @store_i64(i64 %a, ptr %ptr){
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; CHECK-LABEL: store_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x0, [x1]
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; CHECK-NEXT: ret
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store i64 %a, ptr %ptr
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ret void
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}
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; ===== Legal Vector Types =====
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define void @store_v8i8(<8 x i8> %a, ptr %ptr){
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; CHECK-LABEL: store_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str d0, [x0]
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; CHECK-NEXT: ret
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store <8 x i8> %a, ptr %ptr
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ret void
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}
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define void @store_v16i8(<16 x i8> %a, ptr %ptr){
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; CHECK-LABEL: store_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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store <16 x i8> %a, ptr %ptr
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ret void
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}
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define void @store_v4i16(<4 x i16> %a, ptr %ptr){
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; CHECK-LABEL: store_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str d0, [x0]
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; CHECK-NEXT: ret
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store <4 x i16> %a, ptr %ptr
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ret void
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}
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define void @store_v8i16(<8 x i16> %a, ptr %ptr){
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; CHECK-LABEL: store_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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store <8 x i16> %a, ptr %ptr
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ret void
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}
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define void @store_v2i32(<2 x i32> %a, ptr %ptr){
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; CHECK-LABEL: store_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str d0, [x0]
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; CHECK-NEXT: ret
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store <2 x i32> %a, ptr %ptr
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ret void
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}
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define void @store_v4i32(<4 x i32> %a, ptr %ptr){
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; CHECK-LABEL: store_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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store <4 x i32> %a, ptr %ptr
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ret void
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}
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define void @store_v2i64(<2 x i64> %a, ptr %ptr){
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; CHECK-LABEL: store_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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store <2 x i64> %a, ptr %ptr
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ret void
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}
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; ===== Smaller/Larger Width Vectors with Legal Element Sizes =====
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define void @store_v4i8(i32 %a, ptr %ptr) {
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; CHECK-LABEL: store_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str w0, [x1]
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; CHECK-NEXT: ret
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%c = bitcast i32 %a to <4 x i8>
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store <4 x i8> %c, ptr %ptr
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ret void
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}
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define void @store_v32i8(<32 x i8> %a, ptr %ptr){
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; CHECK-LABEL: store_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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store <32 x i8> %a, ptr %ptr
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ret void
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}
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define void @store_v2i16(<2 x i16> %a, ptr %ptr){
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; CHECK-SD-LABEL: store_v2i16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: mov w8, v0.s[1]
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; CHECK-SD-NEXT: fmov w9, s0
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; CHECK-SD-NEXT: strh w9, [x0]
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; CHECK-SD-NEXT: strh w8, [x0, #2]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: store_v2i16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-GI-NEXT: mov s1, v0.s[1]
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; CHECK-GI-NEXT: str h0, [x0]
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; CHECK-GI-NEXT: str h1, [x0, #2]
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; CHECK-GI-NEXT: ret
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store <2 x i16> %a, ptr %ptr
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ret void
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}
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define void @store_v16i16(<16 x i16> %a, ptr %ptr){
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; CHECK-LABEL: store_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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store <16 x i16> %a, ptr %ptr
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ret void
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}
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define void @store_v1i32(<1 x i32> %a, ptr %ptr){
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; CHECK-SD-LABEL: store_v1i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: str s0, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: store_v1i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: str s0, [x0]
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; CHECK-GI-NEXT: ret
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store <1 x i32> %a, ptr %ptr
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ret void
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}
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define void @store_v8i32(<8 x i32> %a, ptr %ptr){
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; CHECK-LABEL: store_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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store <8 x i32> %a, ptr %ptr
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ret void
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}
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define void @store_v4i64(<4 x i64> %a, ptr %ptr){
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; CHECK-LABEL: store_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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store <4 x i64> %a, ptr %ptr
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ret void
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}
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; ===== Vectors with Non-Pow 2 Widths =====
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define void @store_v3i8(<3 x i8> %a, ptr %ptr){
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; CHECK-SD-LABEL: store_v3i8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sub sp, sp, #16
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; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
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; CHECK-SD-NEXT: fmov s0, w0
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; CHECK-SD-NEXT: mov v0.h[1], w1
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; CHECK-SD-NEXT: mov v0.h[2], w2
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; CHECK-SD-NEXT: xtn v0.8b, v0.8h
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; CHECK-SD-NEXT: str s0, [sp, #12]
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; CHECK-SD-NEXT: ldrh w8, [sp, #12]
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; CHECK-SD-NEXT: strb w2, [x3, #2]
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; CHECK-SD-NEXT: strh w8, [x3]
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; CHECK-SD-NEXT: add sp, sp, #16
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: store_v3i8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: strb w0, [x3]
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; CHECK-GI-NEXT: strb w1, [x3, #1]
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; CHECK-GI-NEXT: strb w2, [x3, #2]
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; CHECK-GI-NEXT: ret
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store <3 x i8> %a, ptr %ptr
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ret void
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}
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define void @store_v7i8(<7 x i8> %a, ptr %ptr){
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; CHECK-SD-LABEL: store_v7i8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: add x8, x0, #6
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; CHECK-SD-NEXT: add x9, x0, #4
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: str s0, [x0]
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; CHECK-SD-NEXT: st1 { v0.b }[6], [x8]
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; CHECK-SD-NEXT: st1 { v0.h }[2], [x9]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: store_v7i8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: add x8, x0, #1
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-GI-NEXT: add x9, x0, #2
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; CHECK-GI-NEXT: st1 { v0.b }[0], [x0]
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; CHECK-GI-NEXT: st1 { v0.b }[1], [x8]
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; CHECK-GI-NEXT: add x8, x0, #3
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; CHECK-GI-NEXT: st1 { v0.b }[3], [x8]
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; CHECK-GI-NEXT: add x8, x0, #4
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; CHECK-GI-NEXT: st1 { v0.b }[4], [x8]
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; CHECK-GI-NEXT: add x8, x0, #5
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; CHECK-GI-NEXT: st1 { v0.b }[5], [x8]
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; CHECK-GI-NEXT: add x8, x0, #6
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; CHECK-GI-NEXT: st1 { v0.b }[2], [x9]
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; CHECK-GI-NEXT: st1 { v0.b }[6], [x8]
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; CHECK-GI-NEXT: ret
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store <7 x i8> %a, ptr %ptr
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ret void
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}
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define void @store_v3i16(<3 x i16> %a, ptr %ptr){
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; CHECK-SD-LABEL: store_v3i16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: add x8, x0, #4
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: str s0, [x0]
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; CHECK-SD-NEXT: st1 { v0.h }[2], [x8]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: store_v3i16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: add x8, x0, #2
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; CHECK-GI-NEXT: add x9, x0, #4
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-GI-NEXT: str h0, [x0]
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; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]
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; CHECK-GI-NEXT: st1 { v0.h }[2], [x9]
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; CHECK-GI-NEXT: ret
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store <3 x i16> %a, ptr %ptr
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ret void
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}
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define void @store_v7i16(<7 x i16> %a, ptr %ptr){
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; CHECK-SD-LABEL: store_v7i16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: add x8, x0, #12
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; CHECK-SD-NEXT: add x9, x0, #8
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; CHECK-SD-NEXT: str d0, [x0]
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; CHECK-SD-NEXT: st1 { v0.h }[6], [x8]
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; CHECK-SD-NEXT: st1 { v0.s }[2], [x9]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: store_v7i16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: add x8, x0, #2
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; CHECK-GI-NEXT: add x9, x0, #4
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; CHECK-GI-NEXT: str h0, [x0]
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; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]
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; CHECK-GI-NEXT: add x8, x0, #6
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; CHECK-GI-NEXT: st1 { v0.h }[3], [x8]
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; CHECK-GI-NEXT: add x8, x0, #8
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; CHECK-GI-NEXT: st1 { v0.h }[4], [x8]
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; CHECK-GI-NEXT: add x8, x0, #10
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; CHECK-GI-NEXT: st1 { v0.h }[5], [x8]
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; CHECK-GI-NEXT: add x8, x0, #12
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; CHECK-GI-NEXT: st1 { v0.h }[2], [x9]
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; CHECK-GI-NEXT: st1 { v0.h }[6], [x8]
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; CHECK-GI-NEXT: ret
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store <7 x i16> %a, ptr %ptr
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ret void
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}
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define void @store_v3i32(<3 x i32> %a, ptr %ptr){
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; CHECK-SD-LABEL: store_v3i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: add x8, x0, #8
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; CHECK-SD-NEXT: str d0, [x0]
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; CHECK-SD-NEXT: st1 { v0.s }[2], [x8]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: store_v3i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: add x8, x0, #4
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; CHECK-GI-NEXT: add x9, x0, #8
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; CHECK-GI-NEXT: str s0, [x0]
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; CHECK-GI-NEXT: st1 { v0.s }[1], [x8]
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; CHECK-GI-NEXT: st1 { v0.s }[2], [x9]
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; CHECK-GI-NEXT: ret
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store <3 x i32> %a, ptr %ptr
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ret void
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}

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