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CunningBaldrickCunningBaldrick
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Remove trailing whitespace. Reorder some methods
and cases alphabetically. No functionality change. llvm-svn: 75001
1 parent ca4231e commit 3f1e240

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5 files changed

+60
-59
lines changed

5 files changed

+60
-59
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -491,7 +491,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
491491

492492
SDValue NewVAARG;
493493
NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2));
494-
494+
495495
// Legalized the chain result - switch anything that used the old chain to
496496
// use the new one.
497497
ReplaceValueWith(SDValue(N, 1), NewVAARG.getValue(1));

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -359,7 +359,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
359359
// If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
360360
// not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
361361
// and SINT conversions are Custom, there is no way to tell which is preferable.
362-
// We choose SINT because that's the right thing on PPC.)
362+
// We choose SINT because that's the right thing on PPC.)
363363
if (N->getOpcode() == ISD::FP_TO_UINT &&
364364
!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
365365
TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
@@ -1838,7 +1838,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
18381838
else if (VT == MVT::i128)
18391839
LC = RTLIB::SRA_I128;
18401840
}
1841-
1841+
18421842
if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
18431843
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
18441844
SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -517,10 +517,10 @@ class VISIBILITY_HIDDEN DAGTypeLegalizer {
517517
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
518518
SDValue ScalarizeVecRes_SELECT(SDNode *N);
519519
SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
520+
SDValue ScalarizeVecRes_SETCC(SDNode *N);
520521
SDValue ScalarizeVecRes_UNDEF(SDNode *N);
521522
SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
522523
SDValue ScalarizeVecRes_VSETCC(SDNode *N);
523-
SDValue ScalarizeVecRes_SETCC(SDNode *N);
524524

525525
// Vector Operand Scalarization: <1 x ty> -> ty.
526526
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
@@ -558,10 +558,10 @@ class VISIBILITY_HIDDEN DAGTypeLegalizer {
558558
void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
559559
void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
560560
void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
561+
void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
561562
void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
562-
void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
563+
void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
563564
SDValue &Hi);
564-
void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
565565

566566
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
567567
bool SplitVectorOperand(SDNode *N, unsigned OpNo);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
106106

107107
if (TLI.isBigEndian())
108108
std::swap(Lo, Hi);
109-
109+
110110
return;
111111
}
112112
}

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 53 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -53,10 +53,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
5353
case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
5454
case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
5555
case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
56+
case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
5657
case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
5758
case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
5859
case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
59-
case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
6060

6161
case ISD::CTLZ:
6262
case ISD::CTPOP:
@@ -207,6 +207,15 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
207207
N->getOperand(4));
208208
}
209209

210+
SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
211+
SDValue LHS = GetScalarizedVector(N->getOperand(0));
212+
SDValue RHS = GetScalarizedVector(N->getOperand(1));
213+
DebugLoc DL = N->getDebugLoc();
214+
215+
// Turn it into a scalar SETCC.
216+
return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
217+
}
218+
210219
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
211220
return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
212221
}
@@ -242,7 +251,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
242251
// Truncate to the final type.
243252
return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
244253
}
245-
254+
246255
// The SETCC result type is smaller than the vector element type.
247256
// If the SetCC result is not sign-extended, chop it down to MVT::i1.
248257
if (TLI.getBooleanContents() !=
@@ -251,14 +260,6 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
251260
// Sign extend to the final type.
252261
return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
253262
}
254-
SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
255-
SDValue LHS = GetScalarizedVector(N->getOperand(0));
256-
SDValue RHS = GetScalarizedVector(N->getOperand(1));
257-
DebugLoc DL = N->getDebugLoc();
258-
259-
// Turn it into a scalar SETCC.
260-
return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
261-
}
262263

263264

264265
//===----------------------------------------------------------------------===//
@@ -392,14 +393,13 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
392393
case ISD::LOAD:
393394
SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
394395
break;
395-
case ISD::VECTOR_SHUFFLE:
396-
SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
397-
break;
398-
399-
case ISD::VSETCC:
400396
case ISD::SETCC:
397+
case ISD::VSETCC:
401398
SplitVecRes_SETCC(N, Lo, Hi);
402399
break;
400+
case ISD::VECTOR_SHUFFLE:
401+
SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
402+
break;
403403

404404
case ISD::CTTZ:
405405
case ISD::CTLZ:
@@ -735,6 +735,42 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
735735
ReplaceValueWith(SDValue(LD, 1), Ch);
736736
}
737737

738+
void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
739+
MVT LoVT, HiVT;
740+
DebugLoc DL = N->getDebugLoc();
741+
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
742+
743+
// Split the input.
744+
MVT InVT = N->getOperand(0).getValueType();
745+
SDValue LL, LH, RL, RH;
746+
switch (getTypeAction(InVT)) {
747+
default: assert(0 && "Unexpected type action!");
748+
case WidenVector: assert(0 && "Unimp");
749+
case Legal: {
750+
assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
751+
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
752+
LoVT.getVectorNumElements());
753+
LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
754+
DAG.getIntPtrConstant(0));
755+
LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
756+
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
757+
758+
RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
759+
DAG.getIntPtrConstant(0));
760+
RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
761+
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
762+
break;
763+
}
764+
case SplitVector:
765+
GetSplitVector(N->getOperand(0), LL, LH);
766+
GetSplitVector(N->getOperand(1), RL, RH);
767+
break;
768+
}
769+
770+
Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
771+
Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
772+
}
773+
738774
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
739775
SDValue &Hi) {
740776
// Get the dest types - they may not match the input types, e.g. int_to_fp.
@@ -889,41 +925,6 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
889925
}
890926
}
891927

892-
void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
893-
MVT LoVT, HiVT;
894-
DebugLoc DL = N->getDebugLoc();
895-
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
896-
897-
// Split the input.
898-
MVT InVT = N->getOperand(0).getValueType();
899-
SDValue LL, LH, RL, RH;
900-
switch (getTypeAction(InVT)) {
901-
default: assert(0 && "Unexpected type action!");
902-
case WidenVector: assert(0 && "Unimp");
903-
case Legal: {
904-
assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
905-
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
906-
LoVT.getVectorNumElements());
907-
LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
908-
DAG.getIntPtrConstant(0));
909-
LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
910-
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
911-
912-
RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
913-
DAG.getIntPtrConstant(0));
914-
RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
915-
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
916-
break;
917-
}
918-
case SplitVector:
919-
GetSplitVector(N->getOperand(0), LL, LH);
920-
GetSplitVector(N->getOperand(1), RL, RH);
921-
break;
922-
}
923-
924-
Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
925-
Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
926-
}
927928

928929
//===----------------------------------------------------------------------===//
929930
// Operand Vector Splitting
@@ -1149,7 +1150,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
11491150
case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
11501151
case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
11511152
case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1152-
case ISD::VECTOR_SHUFFLE:
1153+
case ISD::VECTOR_SHUFFLE:
11531154
Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
11541155
break;
11551156
case ISD::VSETCC:
@@ -1464,7 +1465,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
14641465
MaskOps[i] = i;
14651466
MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
14661467
}
1467-
return DAG.getVectorShuffle(WidenVT, dl,
1468+
return DAG.getVectorShuffle(WidenVT, dl,
14681469
GetWidenedVector(N->getOperand(0)),
14691470
GetWidenedVector(N->getOperand(1)),
14701471
&MaskOps[0]);

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