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regen test
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6 files changed

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6 files changed

+22
-15
lines changed

‎llvm/test/Analysis/ScalarEvolution/ashr.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ define i32 @t4(i32 %x, i32 %y) {
5151
; CHECK-LABEL: 't4'
5252
; CHECK-NEXT: Classifying expressions for: @t4
5353
; CHECK-NEXT: %i0 = ashr exact i32 %x, 32
54-
; CHECK-NEXT: --> %i0 U: [0,1) S: [0,1)
54+
; CHECK-NEXT: --> %i0 U: full-set S: full-set
5555
; CHECK-NEXT: Determining loop execution counts for: @t4
5656
;
5757
%i0 = ashr exact i32 %x, 32

‎llvm/test/Analysis/ScalarEvolution/pr76234.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,9 @@ define i32 @PR76234() {
66
; CHECK-LABEL: 'PR76234'
77
; CHECK-NEXT: Classifying expressions for: @PR76234
88
; CHECK-NEXT: %B9 = shl i896 0, -264147265567832623176169892458258303259423663018060761063980354513336951278362429737208627943828593947337197496628564339441173779751342768625269489231469788454193341999502542084365758838213220526512116454105594202074014146375780869419198449383518238244769290448868999168
9-
; CHECK-NEXT: --> %B9 U: [0,1) S: [0,1)
9+
; CHECK-NEXT: --> %B9 U: full-set S: full-set
1010
; CHECK-NEXT: %B39 = ashr i896 %B9, 1
11-
; CHECK-NEXT: --> %B39 U: [0,1) S: [0,1) Exits: <<Unknown>> LoopDispositions: { %1: Variant }
11+
; CHECK-NEXT: --> %B39 U: [-132073632783916311588084946229129151629711831509030380531990177256668475639181214868604313971914296973668598748314282169720586889875671384312634744615734894227096670999751271042182879419106610263256058227052797101037007073187890434709599224691759119122384645224434499584,132073632783916311588084946229129151629711831509030380531990177256668475639181214868604313971914296973668598748314282169720586889875671384312634744615734894227096670999751271042182879419106610263256058227052797101037007073187890434709599224691759119122384645224434499584) S: [-132073632783916311588084946229129151629711831509030380531990177256668475639181214868604313971914296973668598748314282169720586889875671384312634744615734894227096670999751271042182879419106610263256058227052797101037007073187890434709599224691759119122384645224434499584,132073632783916311588084946229129151629711831509030380531990177256668475639181214868604313971914296973668598748314282169720586889875671384312634744615734894227096670999751271042182879419106610263256058227052797101037007073187890434709599224691759119122384645224434499584) Exits: <<Unknown>> LoopDispositions: { %1: Variant }
1212
; CHECK-NEXT: Determining loop execution counts for: @PR76234
1313
; CHECK-NEXT: Loop %1: <multiple exits> Unpredictable backedge-taken count.
1414
; CHECK-NEXT: Loop %1: Unpredictable constant max backedge-taken count.

‎llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,6 @@ legalized: true
6060
body: |
6161
bb.0:
6262
liveins: $w0
63-
; AArch64 needs a constant on the shift for this combine.
6463
6564
; CHECK-LABEL: name: dont_apply_no_constant
6665
; CHECK: liveins: $w0
@@ -87,15 +86,15 @@ body: |
8786
bb.0:
8887
liveins: $w0
8988
90-
; LSB must be in 0-31.
9189
9290
; CHECK-LABEL: name: dont_apply_shift_imm_too_large
9391
; CHECK: liveins: $w0
9492
; CHECK-NEXT: {{ $}}
9593
; CHECK-NEXT: %x:_(s32) = COPY $w0
9694
; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 32
9795
; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
98-
; CHECK-NEXT: $w0 = COPY %shift(s32)
96+
; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
97+
; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
9998
; CHECK-NEXT: RET_ReallyLR implicit $w0
10099
%x:_(s32) = COPY $w0
101100
%lsb:_(s32) = G_CONSTANT i32 32
@@ -113,15 +112,15 @@ body: |
113112
bb.0:
114113
liveins: $w0
115114
116-
; LSB must be in 0-31.
117115
118116
; CHECK-LABEL: name: dont_apply_negative_shift_imm
119117
; CHECK: liveins: $w0
120118
; CHECK-NEXT: {{ $}}
121119
; CHECK-NEXT: %x:_(s32) = COPY $w0
122120
; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 -1
123121
; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
124-
; CHECK-NEXT: $w0 = COPY %shift(s32)
122+
; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
123+
; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
125124
; CHECK-NEXT: RET_ReallyLR implicit $w0
126125
%x:_(s32) = COPY $w0
127126
%lsb:_(s32) = G_CONSTANT i32 -1

‎llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ define amdgpu_kernel void @write_ds_sub_max_offset_global_clamp_bit(float %dummy
138138
; CI-NEXT: s_load_dword s0, s[0:1], 0x0
139139
; CI-NEXT: s_mov_b64 vcc, 0
140140
; CI-NEXT: v_mov_b32_e32 v1, 0x7b
141-
; CI-NEXT: v_mov_b32_e32 v2, 0
141+
; CI-NEXT: v_mov_b32_e32 v2, -1
142142
; CI-NEXT: s_mov_b32 m0, -1
143143
; CI-NEXT: s_waitcnt lgkmcnt(0)
144144
; CI-NEXT: v_mov_b32_e32 v0, s0
@@ -157,7 +157,7 @@ define amdgpu_kernel void @write_ds_sub_max_offset_global_clamp_bit(float %dummy
157157
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x0
158158
; GFX9-NEXT: s_mov_b64 vcc, 0
159159
; GFX9-NEXT: v_mov_b32_e32 v3, 0x7b
160-
; GFX9-NEXT: v_mov_b32_e32 v4, 0
160+
; GFX9-NEXT: v_mov_b32_e32 v4, -1
161161
; GFX9-NEXT: ds_write_b32 v4, v3
162162
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
163163
; GFX9-NEXT: v_mov_b32_e32 v0, s0
@@ -174,7 +174,7 @@ define amdgpu_kernel void @write_ds_sub_max_offset_global_clamp_bit(float %dummy
174174
; GFX10-NEXT: s_mov_b32 vcc_lo, 0
175175
; GFX10-NEXT: v_mov_b32_e32 v0, 0
176176
; GFX10-NEXT: v_mov_b32_e32 v2, 0x7b
177-
; GFX10-NEXT: v_mov_b32_e32 v3, 0
177+
; GFX10-NEXT: v_mov_b32_e32 v3, -1
178178
; GFX10-NEXT: v_mov_b32_e32 v1, 0
179179
; GFX10-NEXT: ds_write_b32 v3, v2
180180
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -188,7 +188,7 @@ define amdgpu_kernel void @write_ds_sub_max_offset_global_clamp_bit(float %dummy
188188
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
189189
; GFX11-NEXT: s_mov_b32 vcc_lo, 0
190190
; GFX11-NEXT: v_mov_b32_e32 v0, 0
191-
; GFX11-NEXT: v_dual_mov_b32 v2, 0x7b :: v_dual_mov_b32 v3, 0
191+
; GFX11-NEXT: v_dual_mov_b32 v2, 0x7b :: v_dual_mov_b32 v3, -1
192192
; GFX11-NEXT: v_mov_b32_e32 v1, 0
193193
; GFX11-NEXT: ds_store_b32 v3, v2
194194
; GFX11-NEXT: s_waitcnt lgkmcnt(0)

‎llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -139,7 +139,11 @@ define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {
139139

140140
define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) {
141141
; CHECK-LABEL: @test_shl_nuw_nsw__nsw_is_safe(
142-
; CHECK-NEXT: ret i32 0
142+
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
143+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
144+
; CHECK-NEXT: [[DOTNEG:%.*]] = select i1 [[TMP2]], i32 335544316, i32 1
145+
; CHECK-NEXT: [[DOTNEG1:%.*]] = mul i32 [[DOTNEG]], [[TMP1]]
146+
; CHECK-NEXT: ret i32 [[DOTNEG1]]
143147
;
144148
%1 = or i32 %x, -83886080
145149
%2 = icmp eq i32 %1, -83886079
@@ -152,7 +156,11 @@ define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) {
152156

153157
define i32 @test_shl_nuw__nsw_is_safe(i32 %x) {
154158
; CHECK-LABEL: @test_shl_nuw__nsw_is_safe(
155-
; CHECK-NEXT: ret i32 0
159+
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
160+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
161+
; CHECK-NEXT: [[DOTNEG:%.*]] = select i1 [[TMP2]], i32 335544316, i32 1
162+
; CHECK-NEXT: [[DOTNEG1:%.*]] = mul i32 [[DOTNEG]], [[TMP1]]
163+
; CHECK-NEXT: ret i32 [[DOTNEG1]]
156164
;
157165
%1 = or i32 %x, -83886080
158166
%2 = icmp eq i32 %1, -83886079

‎llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -370,7 +370,7 @@ define i64 @alac_seek(ptr %0) {
370370
; CHECK-SAME: (ptr [[TMP0:%.*]]) {
371371
; CHECK-NEXT: entry:
372372
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 1, 0
373-
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[DIV]], 1
373+
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[DIV]], 1
374374
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP0]], i64 12
375375
; CHECK-NEXT: br label [[FOR_BODY_I:%.*]]
376376
; CHECK: for.body.i:

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