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[clang][RISCV] Change default abi with f extension but without d extension (#73489)
Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f and not d, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent.
1 parent 9cdb825 commit 3fe8141

14 files changed

+45
-38
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‎clang/docs/ReleaseNotes.rst

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@@ -968,6 +968,9 @@ RISC-V Support
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- Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the
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aliases ``-m[no-]strict-align``.
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- Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f
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for RV64.
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CUDA/HIP Language Changes
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^^^^^^^^^^^^^^^^^^^^^^^^^
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‎clang/test/Driver/riscv-abi.c

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@@ -4,8 +4,6 @@
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// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
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// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
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// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
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// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
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// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \
@@ -24,6 +22,10 @@
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// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
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// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
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// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
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// CHECK-ILP32F: "-target-abi" "ilp32f"
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@@ -51,16 +53,18 @@
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// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
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// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
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// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
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// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
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// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \
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// RUN: -mabi=lp64 2>&1 | FileCheck -check-prefix=CHECK-LP64 %s
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// CHECK-LP64: "-target-abi" "lp64"
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// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \
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// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
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// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
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// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \
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// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
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// CHECK-LP64F: "-target-abi" "lp64f"

‎clang/test/Driver/riscv-cpus.c

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@@ -113,15 +113,15 @@
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// MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
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// MCPU-SIFIVE-E24: "-target-feature" "+c"
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// MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
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// MCPU-SIFIVE-E24: "-target-abi" "ilp32"
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// MCPU-SIFIVE-E24: "-target-abi" "ilp32f"
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// mcpu with default march
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s
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// MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34"
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// MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
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// MCPU-SIFIVE-E34: "-target-feature" "+c"
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// MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
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// MCPU-SIFIVE-E34: "-target-abi" "ilp32"
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// MCPU-SIFIVE-E34: "-target-abi" "ilp32f"
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// mcpu with mabi option
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
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// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
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// MCPU-SIFIVE-E76: "-target-feature" "+c"
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// MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
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// MCPU-SIFIVE-E76: "-target-abi" "ilp32"
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// MCPU-SIFIVE-E76: "-target-abi" "ilp32f"
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// mcpu with mabi option
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s

‎llvm/docs/ReleaseNotes.rst

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@@ -140,6 +140,7 @@ Changes to the RISC-V Backend
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* The Zfa extension version was upgraded to 1.0 and is no longer experimental.
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* Zihintntl extension version was upgraded to 1.0 and is no longer experimental.
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* Intrinsics were added for Zk*, Zbb, and Zbc. See https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#scalar-bit-manipulation-extension-intrinsics
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* Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f for RV64.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp

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@@ -1292,12 +1292,16 @@ StringRef RISCVISAInfo::computeDefaultABI() const {
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if (XLen == 32) {
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if (hasExtension("d"))
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return "ilp32d";
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if (hasExtension("f"))
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return "ilp32f";
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if (hasExtension("e"))
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return "ilp32e";
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return "ilp32";
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} else if (XLen == 64) {
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if (hasExtension("d"))
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return "lp64d";
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if (hasExtension("f"))
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return "lp64f";
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if (hasExtension("e"))
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return "lp64e";
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return "lp64";

‎llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=ILP32
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=LP64
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=ILP32F

‎llvm/test/CodeGen/RISCV/calling-conv-half.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F
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; RUN: llc -mtriple=riscv32 -mattr=+f,+zfhmin -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN

‎llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IF
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; Exercises the ILP32 calling convention code in the case that f32 is a legal

‎llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64LP64F %s

‎llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfinx -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IZFINX %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfinx -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IZFINX %s
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; This file tests cases where simple floating point operations can be

‎llvm/test/CodeGen/RISCV/float-frem.ll

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@@ -19,12 +19,7 @@ define float @frem_f32(float %a, float %b) nounwind {
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;
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; RV64IF-LABEL: frem_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call fmodf@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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; RV64IF-NEXT: tail fmodf@plt
2823
;
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; RV32IZFINX-LABEL: frem_f32:
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; RV32IZFINX: # %bb.0:

‎llvm/test/CodeGen/RISCV/float-select-verify.ll

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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+f -stop-after=finalize-isel < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -stop-after=finalize-isel < %s | FileCheck %s
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define dso_local void @buz(i1 %pred, float %a, float %b) {
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; CHECK-LABEL: name: buz

‎llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
4-
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
4+
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfh -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
8+
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfh -verify-machineinstrs \
99
; RUN: < %s | FileCheck -check-prefix=RV64IZFH %s
10-
; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
10+
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx -verify-machineinstrs \
1111
; RUN: < %s | FileCheck -check-prefix=RV32IZHINX %s
12-
; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
12+
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV64IZHINX %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV32IZFHMIN %s
16-
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV64IZFHMIN %s
20-
; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
20+
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin -verify-machineinstrs \
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; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV32IZHINXMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
22+
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin -verify-machineinstrs \
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; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV64IZHINXMIN %s
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; This file tests cases where simple floating point operations can be

‎llvm/test/CodeGen/RISCV/half-fcmp.ll

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@@ -8,17 +8,17 @@
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; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
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; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
1010
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
11-
; RUN: < %s | FileCheck -check-prefix=RV32I %s
11+
; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
13-
; RUN: < %s | FileCheck -check-prefix=RV64I %s
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; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
1515
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
19-
; RUN: < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
19+
; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
21-
; RUN: < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
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; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
2323
; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \

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